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參數(shù)資料
| 型號： | IDT72T54262L5BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 512K X 10 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 24/56頁 |
| 文件大小： | 555K |
| 代理商： | IDT72T54262L5BBI |
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24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
rising edge of WCLK. In this mode, the data setup and hold times are referenced
with respect to the rising and falling edge of WCLK. Note that
WEN
and
WCS
are sampled only on the rising edge of WCLK in either data rates.
Data is stored in the FIFOs’ memory sequentially and independently of any
ongoing read operation. When the write enables or write chip selects are HIGH,
no new data is written into the corresponding FIFO on each WCLK cycle. Each
write enable operates independently of the others. In Dual mode, the unused
write enables (
WEN
1 and
WEN
3) should be tied to V
CC
.
WRITE CHIP SELECT (
WCS
0/1/2/3)
There are a total of four write chip selects (or two in Dual mode) available
in this device depending on the mode selected, one for each individual FIFO.
The write chip selects disables all data bus inputs if it is held HIGH. To perform
normal write operations, the write chip select must be enabled, (held LOW). The
four write chip selects are completely independent of one another. When the
write chip select is LOW on the rising edge of WCLK in single data rate mode,
data is loaded on the rising edge of every WCLK cycle, provided the device
is not full and the write enable (
WEN
) of the corresponding FIFO is LOW.
When the write chip select is LOW on the rising edge of WCLK in double data
rate mode, data is loaded into any of the FIFOs on the rising and falling edge
of every WCLK cycle, provided the device is not full and the write enable (
WEN
)
of the corresponding FIFO is LOW on the rising clock edge.
When the write chip select is HIGH on the rising edge of WCLK in single data
rate mode, the write port is disabled and no words are written into the FIFO
memory, on the rising edge of WCLK, even if
WEN
is LOW. If the write chip select
is HIGH on the rising edge of WCLK in double data rate mode, the write port
is disabled and no words are written into the FIFO memory on the rising or falling
edge of WCLK, even if
WEN
is LOW. Note that
WCS
is sampled on the rising
edge of WCLK only in either data rate. In Dual mode, the unused write chip
selects (
WCS
1 and
WCS
3) should be tied to V
CC
.
WRITE DOUBLE DATA RATE (WDDR)
When the write double data rate (WDDR) pin is HIGH, the write port will be
set to double data rate mode. In this mode, all write operations are based on
the rising and falling edge of the write clocks, provided that write enables and
write chip selects are LOW for the rising clock edges. In double data rate the write
enable signals are sampled with respect to the rising edge of write clock only,
and a word will be written to both the rising and falling edge of write clock
regardless of whether or not write enable is active on the falling edge of write
clock.
When WDDR is LOW, the write port will be set to single data rate mode. In
this mode, all write operations are based on only the rising edge of the write
clocks, provided that write enables and write chip selects are LOW during the
rising edge of write clock. This pin should be tied HIGH or LOW and cannot
toggle.
READ CLOCK (RCLK0/1/2/3)
There are a total of four read clocks (or two in Dual mode) available in this
device depending on the mode selected, each corresponding to the individual
FIFOs in memory. A read can be initiated on the rising (or falling) edge of the
RCLK input. If the read double data rate (RDDR) mode pin is tied HIGH, data
will be read on both the rising and falling edge of RCLK0/1/2/3, provided that
REN
0/1/2/3 and
RCS
0/1/2/3 are enabled on the rising edge of RCLK0/1/2/
3. If RDDR is tied LOW, data will be read only on the rising edge of RCLK0/1/
2/3 provided that
REN
0/1/2/3 and
RCS
0/1/2/3 are enabled. Each read clock
is completely independent fromthe others.
There is an associated data access time (t
A
) for the data to be read out of the
FIFOs. It is permssible to stop the read clocks. Note that while the read clocks
are idle, the
EF
/0/1/2/3 and
PAE
0/1/2/3 flags will not be updated unless the part
is operating in asynchronous timng mode (PFM=0). The write and read clocks
can be independent or coincident. In Dual mode, the unused clocks (RCLK1
and RCLK3) should be tied to GND.
READ ENABLE (
REN
0/1/2/3)
There are a total of four read enables (or two in Dual mode) available in this
device depending on the mode selected, one for each individual FIFOs . When
the read enable input is LOW on the rising edge of RCLK in single data rate mode,
data will be read on the rising edge of every RCLK cycle, provided the device
is not empty and the read chip select (
RCS
) is enabled. The associated data
access time (t
A
) is referenced with respect to the rising edge of RCLK. When
the read enable input is LOW on the rising edge of WCLK in double data rate
mode, data will be read on the rising and falling edge of every RCLK cycle,
provided the device is not empty and
RCS
is enabled. In this mode, the data
access times are referenced with respect to the rising and falling edges of RCLK.
Note that
REN
, and
RCS
are sampled only on the rising edge of RCLK in either
data rate.
Data read fromthe FIFO's memory sequentially and independently of any
ongoing write operation. When the read enables or read chip selects are HIGH,
no new data is read on each RCLK cycle. Each read enable operates
independently of the others.
To prevent reading froman empty FIFO in the IDT Standard mode, the empty
flag of each FIFO will go LOW with respect to RCLK, when the total number of
words in the FIFO has been read, thus inhibiting further read operations. Upon
the completion of a valid write cycle, the empty flag will go HIGH with respect
to RCLK two cycles later, thus allowing another read to occur simlarly, for FWFT
mode, the output ready flag of each FIFO will go HIGH with respect to RCLK
when the total number of words in the FIFO has been read out. In Dual mode,
the unused read enables (
REN
1 and
REN
3) should be tied to V
CC
.
READ CHIP SELECT (
RCS
0/1/2/3)
There are a total of four read chip selects (or two in Dual mode) available
in this device, each corresponding to an individual FIFO. The read chip select
inputs provide synchronous control of the read port. When the read chip select
is held LOW, the next rising edge of the corresponding RCLK will enable the
output bus. When the read chip select goes HIGH, the next rising edge of RCLK
will send the output bus into high-impedance and prevent that RCLK from
initiating a read, regardless of the state of
REN
. During a master or partial reset
the read chip select input has no effect on the output bus– output enable is the
only input that provides high-impedance control of the output bus. If output enable
is LOW, the data outputs will be active regardless of read chip select until the first
rising edge of RCLK after a reset is complete. Afterwards if read chip select is
HIGH the data outputs will go to high-impedance. Each read chip select is
completely independent of the others.
The read chip select inputs do not affect the updating of the flags. For example,
when the first word is written to any/all empty FIFOs, the empty flags will still go
fromLOW to HIGH based on a rising edge of the RCLK, regardless of the state
of the read chip select inputs. Also, when operating the FIFO in FWFT mode
the first word written to any/all empty FIFOs will still be clocked through to the
output bus on the third rising edge of RCLK, regardless of the state of read chip
select inputs, assumng that the t
SKEW
parameter is met. For this reason the user
should pay extra attention to the read chip selects when a data word is written
to any/all empty FIFOs in FWFT mode. If the read chip select inputs are HIGH
when an empty FIFO is written into, the first word will fall through to the output
register but will not be available on the outputs because they are in high-
impedance. The user must enable read chip select on the rising edge of RCLK
while disabling
REN
to access this first word. In Dual mode, the unused read
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| IDT72T54242 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT72T54262L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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| IDT72T55248L5BB | 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72T55248L6-7BB | 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
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