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參數(shù)資料
| 型號(hào)： | IDT72T54262L5BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 512K X 10 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | IDT72T54262L5BBI |
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21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
SELECTABLE MODES
This device is capable of operating in two different modes: Quad mode or Dual
mode.
In the Quad mode there are four independent FIFOs available, with the
input and output bus widths set to 10 bits wide for each FIFO.
A total of eight
independent clock inputs are available– four RCLKs and four WCLKs.
Each
FIFO has independent read and write controls, output enable controls, as well
as individual status flags
EF
/
OR
,
FF
/
IR
,
PAE
, and
PAF
.
Also available are echo
outputs ERCLK and
EREN
for each individual FIFO to aid high-speed operation
where synchronizing data is critical.
In the Dual mode there are two independent FIFOs available, with the input
and output bus widths each selectable between x10 or x20.
Bus-matching is
available in this mode, allowing for more flexibility.
A total of four independent
clock inputs are available, two RCLKs and two WCLKs. Each FIFO has
independent read and write controls– output enable controls, as well as
individual status flags
EF
/
OR
,
FF
/
IR
,
PAE
, and
PAF
.
Also available are echo
outputs ERCLK and
EREN
for each individual FIFO to aid high-speed operation
where synchronizing data is critical.
HSTL/LVTTL I/O
The inputs and outputs of this device can be configured for either LVTTL or
HSTL/eHSTL operation.
If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels.
To select between HSTL or eHSTL V
REF
must be
driven to 1.5V or 1.8V respectively. Typically a logic HIGH in HSTL would be
V
REF
+ 0.2V and a logic LOW would be V
REF
– 0.2V.
If the IOSEL pin is LOW during master reset, then all applicable LVTTL or
HSTL signals will be configured for LVTTL operating voltage levels.
In this
configuration V
REF
must be set to GND.
Table 5 illustrates which pins are and
LVTTL/HSTL/eHSTL SELECT
JTAG
TCK
TRST
TMS
TDI
TDO
STATIC CMOS SIGNALS
Static Pins
IOSEL
IW
OW
MD
PFM
RDDR
WDDR
Write Port
D[39:0]
WCLK0/1/2/3
WEN
0/1/2/3
WCS
0/1/2/3
FF
/
IR
0/1/2/3
PAF
0/1/2/3
Read Port
Q[39:0]
RCLK0/1/2/3
REN
0/1/2/3
RCS
0/1/2/3
EF
/
OR
0/1/2/3
OE
0/1/2/3
PAE
0/1/2/3
ERCLK0/1/2/3
EREN
0/1/2/3
Signal Pins
FSEL[1:0]
PD
MRS
PRS
0/1/2/3
FWFT/SI
Serial Clock Port
SCLK
SREN
SWEN
FWFT/SI
SDO
TABLE 5 — I/O VOLTAGE LEVEL ASSOCIATIONS
are not associated with this feature. Note that all “Static Pins” must be tied to V
CC
or GND. These pins are LVTTL only and are purely device configuration pins.
Note the IOSEL pin should be tied HIGH or LOW and cannot toggle before and
after master reset.
BUS MATCHING
In the Dual mode operation, the write and read port have bus-matching
capability such that the input and output busses can each be either 10 bits or
20 bits wide.
The bus width of both the input and output port is determned during
master reset using the input (IW) and output (OW) widths setup pins.
The selected
port width is applied to both FIFO ports, such that both FIFOs will be configured
for either x10 or x20 bus widths. When writing or reading data froma FIFO the
number of memory locations available to be read will depend on the bus width
selected and the density of the device.
If the write/read ports are 10 bits wide, this provides the user with a FIFO depth
of 32,768 x 10 for the IDT72T54242, 65,536 x 10 for the IDT72T54252, or
131,072 x 10 for the IDT72T54262. If the write/read ports are 20 bits wide, this
provides the user with a FIFO depth of 16,384 x 20 for the IDT72T54242,
32,768 x 20 for the IDT72T54252, or 65,536 x 20 for the IDT72T54262. The
FIFO depths will always have a fixed density of 327,680 bits for the IDT72T54242,
655,360 bits for the IDT72T54252 and 1,310,072 bits for the IDT72T54262
regardless of bus-width configuration on the write/read port.
When the device
is operating in double data rate, the word is twice as large as in single data rate
since one word consists of both the rising and falling edge of clock. Therefore
in DDR, the FIFO depths will be half of what it is mentioned above. For instance,
if the write/read port is 10 bits wide, the depth of each FIFO is 16,384 x 10 for
the IDT72T54242, 32,768 x 10 for the IDT72T54252, or 65,536 x 10 for the
IDT72T54262. See Figure 5,
Bus-Matching in Dual mode
for more information.
NOTE:
1. In Dual mode, not all available signals will be used. Signals with a designation of 1 and 3 are not used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T54242 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54242L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T54262L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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