參數(shù)資料
型號(hào)： IDT723646
廠商： Integrated Device Technology, Inc.
英文描述： CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
中文描述： 三重總線SyncFIFO的CMOS與巴士線匹配
文件頁(yè)數(shù)： 5/35頁(yè)
文件大?。?/td> 563K
代理商： IDT723646
5
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
PIN DESCRIPTIONS (CONTINUED)
Symbol
Name
I/O
FS1/
SEN
Flag Offset
I
FS1/
SEN
and FS0/SD are dual-purpose inputs used for flag Offset register programmng. During Master Reset,
Select 1/
FS1/
SEN
and FS0/SD, together with
SPM
, select the flag offset programmng method. Three Offset register
Serial Enable,
programmng methods are available: automatically load one of three preset values (8, 16, or 64), parallel load
fromPort A, and serial FS0/SD load.
Flag Offset
I
Select 0/
When serial load is selected for flag Offset register programmng, FS1/
SEN
is used as an enable synchronous to
Serial Data
the LOW-to-HIGH transition of CLKA. When FS1/
SEN
is LOW, a rising edge on CLKA load the bit present on
FS0/SD into the X and Y registers. The number of bit writes required to programthe Offset registers is 32 for the
IDT723626, 36 for the IDT723636, and 40 for the IDT723646. The first bit write stores the Y-register (Y1) MSB
and the last bit write stores the X-register (X2) LSB.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs
Select
are active, a HIGH level on MBA selects data fromthe mail2 register for output and a LOW level selects FIFO2
output-register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are
Select
active, a HIGH level on MBB selects data fromthe mail1 register for output and a LOW level selects FIFO1 output
register data for output.
MBC
Port C Mailbox
I
A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during
Select
Master Reset.
MBF1
Mail1 Register Flag
O
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1
register are inhibited while
MBF1
is LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB when a
Port B read is selected and MBB is HIGH.
MBF1
is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register Flag
O
MBF2
is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2
register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH.
MBF2
is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
Master Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on
MRS1
selects the programmng method (serial or parallel)
and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and C for bus size
and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while
MRS1
is LOW.
MRS2
Master Reset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output
register to all zeroes. A LOW-to-HIGH transition on
MRS2
toggled simultaneously with
MRS1
, selects the programmng
method (serial or parallel) and one of the three flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA
and four LOW-to-HIGH transitions of CLKC must occur while
MRS2
is LOW.
PRS1
Partial Reset
I
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programmng
method (serial or parallel), and programmable flag settings are all retained.
PRS2
Partial Reset
I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A
output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programmng
method (serial or parallel), and programmable flag settings are all retained.
RENB
Port B Read Enable I
RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B.
SIZEB
(1)
Port B
I
SIZEB determnes the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select
selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement for
ports B and C. The level of SIZEB must be static throughout device operation.
SIZEC
(1)
Port C
I
SIZEC determnes the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin
Bus Size Select
selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement for
ports B and C. The level of SIZEC must be static throughout device operation.
SPM
(1)
Serial Programmng
I
A LOW on this pin selects serial programmng of partial flag offsets. A HIGH on this pin selects parallel programmng
Mode
or default offsets (8, 16, or 64).
WENC
Port C Write Enable
I
WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C.
W/
R
A
Port A Write/Read
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of
Select
CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
R
A is HIGH.
NOTE:
1. SIZEB, SIZEC and
SPM
are not TTL compatible. These inputs should be tied to GND or VCC.
COMMERCIAL TEMPERATURE RANGE
Description
相關(guān)PDF資料
PDF描述
IDT723646L12PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723646L15PF CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING
IDT723626L12PF Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
IDT723626L15PF Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723646L12PF 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT723646L12PF8 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT723646L15PF 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT723646L15PF8 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT723651L15PF 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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