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參數(shù)資料
| 型號(hào)： | IDT723646 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| 中文描述： | 三重總線SyncFIFO的CMOS與巴士線匹配 |
| 文件頁數(shù)： | 15/35頁 |
| 文件大?。?/td> | 563K |
| 代理商： | IDT723646 |
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15
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
data appear on A18-A35. (In this case, A0-A17 are indetermnate.) For a 9-
bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case, A0-A17
and A27-A35 are indetermnate.)
The data in a mail register remains intact after it is read and changes only
when new data is written to the register. The Endian Select feature has no effect
on mailbox data.
Note that MBC must be HIGH during Master Reset (until
FFA
/IRA and
FFC/
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail registers and mail register flag timng diagrams, see Figure 28 and 29.
BUS SIZING
Port B may be configured in either an 18-bit word or a 9-bit byte format
for data read fromFIFO1. Port C may be configured in either an 18-bit word
or a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determnes the Port B bus size and the level applied to the
Port C Size Select (SIZEC) input determnes the Port C bus size. These
levels should be static throughout FIFO operation. Both bus size selections
are implemented at the completion of Master Reset, by the time the Full/
Input Ready flag is set HIGH, as shown in Figures 2 and 3.
Two different methods for sequencing data transfer are available for
Ports B and C regardless of whether the bus size selection is byte- or word-
size. They are referred to as Big-Endian (most significant byte first) and
Little-Endian (least significant byte first). The level applied to the Big-
Endian Select (BE) input during the LOW-to-HIGH transition of
MRS1
and
MRS2
selects the endian method that will be active during FIFO operation. This
selection applies to both ports B and C. The endian method is implemented at
the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH,
as shown in Figures 2 and 3 (see Endian Selection section).
Only 36-bit long word data is written to or read fromthe two FIFO memories
on these devices. Bus-matching operations are done after data is read fromthe
FIFO1 RAM(Port B) and before data is written to the FIFO2 RAM(Port C)
.
The Endian Select operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size bus selections limt
the width of the data bus that can be used for mail register operations. In this case,
only those byte lanes belonging to the selected word- or byte-size bus can carry
mailbox data. The remaining data outputs will be indetermnate. The remaining
data inputs will be dont care inputs. For example, when a word-size bus is
selected on Port B, then mailbox data can be transmtted only fromA0-A17 to
B0-B17. When a byte-size bus is selected on Port B, then mailbox data can be
transmtted only fromA0-A8 to B0-B8. Simlarly, when a word-size bus is
selected on Port C, then mailbox data can be transmtted only fromC0-C17 to
A18-A35. When a byte-size bus is selected on Port C, then mailbox data can
be transmtted only fromC0-C8 to A18-A26. (See Figures 28 and 29).
BUS-MATCHING FIFO1 READS
Data is read fromthe FIFO1 RAMin 36-bit long word increments. Since
Port B can have a byte or word size, only the first one or two bytes appear
on the selected portion of the FIFO1 output register, with the rest of the long
word stored in auxiliary registers. In this case, subsequent FIFO1 reads
output the rest of the long word to the FIFO1 output register in the order
shown by Figure 2.
When reading data fromFIFO1 in byte format, the unused B9-B17
outputs are indetermnate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAMin 36-bit long word increments. Data
written to FIFO2 with a byte or word bus size stores the initial bytes or words
in auxiliary registers. The CLKC rising edge that writes the fourth byte or the
second word of long word to FIFO2 also stores the entire long word in the
FIFO2 memory. The bytes are arranged in the manner shown in Figure 3.
When writing data to FIFO2 in byte format, the unused C9-C17 inputs
are don't care inputs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT723646L12PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723646L15PF | CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING |
| IDT723626L12PF | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| IDT723626L15PF | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| IDT723636 | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC -40 to 105 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723646L12PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723646L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723646L15PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723646L15PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723651L15PF | 功能描述:IC FIFO SYNC 2048X36 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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