參數(shù)資料
型號(hào)： IDT723632L15PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： CMOS SyncBiFIFOO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
中文描述： 512 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120
封裝： TQFP-120
文件頁(yè)數(shù)： 4/26頁(yè)
文件大小： 294K
代理商： IDT723632L15PF
5.22
4
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
AEA
Port-A Data
Port-A Almost
-Empty Flag
I/0
O
36-bit bidirectional data port for side A.
Programmable almost-empty flag synchronized to CLKA. It is LOW
when the number of words in FIF02 is less than or equal to the value in the
almost-empty A offset register, X2.
Programmable almost-empty flag synchronzed to CLKB. It is LOW
when the number of words in FIF01 is less than or equal to the value in the
almost-empty B offset register, X1.
Programmable almost-full flag synchronized to CLKA. It is LOW when
the number of empty locations in FIF01 is less than or equal to the value in
the almost-full A offset register, Y1.
Programmable almost-full flag synchronized to CLKB. It is LOW when
the number of empty locations in FIF02 is less than or equal to the value in
the almost-full B offset register, Y2.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A
and can be asynchronous or coincident to CLKB. IRA, ORA,
AFA
, and
AEA
are all synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B
and can be asynchronous or coincident to CLKA. IRB, ORB,
AFB
, and
AEB
are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable to LOW-to-HIGH transition of CLKA to read or
write on port A. The AO-A35 outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or
write data on port B. The BO- B35 outputs are in the high-impedance state
when
CSB
is HIGH.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or
write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or
write data on port B.
The LOW-to-HIGH transition of a FlFO’s reset input latches the values of FSO
and FS1. If either FSO or FS1 is HIGH when a reset input goes HIGH, one
of the three preset values is selected as the offset for the FlFOs almost-full
and almost-empty flags. If both FIFOs are reset simultaneously and both FSO
and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to
FIFO1 almost empty offsets for both FlFOs.
IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is
LOW, FIFO1 is full and writes to its array are disabled. IRA is set LOW
when FIFO1 is reset and is set HIGH on the second LOW-to-HIGH transition
of CLKA after reset.
IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is
LOW, FIFO2 is full and writes to its array are disabled. IRB is set LOW when
FIFO2 is reset and is set HIGH on the second LOW-to-HIGH transition of
CLKB after reset.
A HIGH level on MBA chooses a mailbox register for a port-A read or
write operation. When the AO-A35 outputs are active, a HIGH level on MBA
selects data from the mail2 register for output and a LOW level selects FIF02
output-register data for output.
(Port A)
AEB
Port-B Almost
-Empty Flag
O
(Port B)
AFA
Port-A Almost
-Full Flag
O
(Port A)
AFB
Port-B Almost
-Full Flag
O
(Port B)
B0 - B35
CLKA
Port-B Data
Port-A Clock
I/O
I
CLKB
Port-B Clock
I
CSA
Port-A Chip
Select
I
CSB
Port-B Chip
Select
I
ENA
Port-A Enable
I
ENB
Port-B Enable
I
FS1,
FS0
Flag Offset
Selects
I
IRA
Input-Ready
Flag
O
(Port A)
IRB
Input-Ready
Flag
O
(Port B)
MBA
Port-A Mailbox
Select
I
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT723632L15PF8 功能描述:IC FIFO SYNC 512X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723632L15PQF 功能描述:IC FIFO SYNC 512X36X2 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT723633L12PF 功能描述:IC FIFO SYNC 512X36 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723633L12PF8 功能描述:IC FIFO SYNC 512X36 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT723633L15PF 功能描述:IC FIFO SYNC 512X36 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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