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參數資料
| 型號： | IDT723632L15PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS SyncBiFIFOO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2 |
| 中文描述： | 512 X 36 BI-DIRECTIONAL FIFO, 10 ns, PQFP120 |
| 封裝： | TQFP-120 |
| 文件頁數： | 11/26頁 |
| 文件大?。?/td> | 294K |
| 代理商： | IDT723632L15PF |
5.22
11
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
CSA
W/
R
A
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
↑
↑
X
↑
X
↑
A0-A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO2 output register
Active, FIFO2 output register
Active, mail2 register
Active, mail2 register
PORT FUNCTION
None
None
FIFO1 write
Mail1 write
None
FIFO2 read
None
Mail2 read (set
MBF2
HIGH)
H
L
L
L
L
L
L
L
CSB
W
/RB
X
L
L
L
H
H
H
H
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
↑
↑
X
↑
X
↑
B0-B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO1 output register
Active, FIFO1 output register
Active, mail1 register
Active, mail1 register
PORT FUNCTION
None
None
FIFO2 write
Mail2 write
None
FIFO1 read
None
Mail1 read (set
MBF1
HIGH)
H
L
L
L
L
L
L
L
Table 3. Port-B Enable Function Table
Table 2. Port-A Enable Functlon Table
port-B operation.
The port-B control signals are identical to those of port A
with the exception that the port-B write/read select (
W
/RB) is
the inverse of the port-A write/read select (W/
R
A). The state
of the port-B data (B0-B35) outputs is controlled by the port-
B chip select (
CSB
) and port-B write/read select (
W
/RB). The
B0-B35 outputs are in the high-impedance state when either
CSB
is HIGH or
W
/RB is LOW. The B0-B35 outputs are active
when
CSB
is LOW and
W
/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a
LOW-to-HIGH transition of CLKB when
CSB
is LOW,
W
/RB is
LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is
read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when
CSB
is LOW,
W
/RB is HIGH, ENB is
HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO
reads and writes on port B are independent of any concurrent
port-A operation.
The setup and hold time constraints to the port clocks for
the port chip selects and write/read selects are only for
enabling write and read operations and are not related to high-
impedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port’s chip select and write/read
select may change states during the setup and hold time
window of the cycle.
When a FIFO output-ready flag is LOW, the next data
word is sent to the FIFO output register automatically by the
LOW-to-HIGH transition of the port clock that sets the output-
ready flag HIGH. When the output-ready flag is HIGH, an
available data word is clocked to the FIFO output register only
when a FIFO read is selected by the port’s chip select, write/
read select, enable, and mailbox select.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at
least two flip-flop stages. This is done to improve flag-signal
reliability by reducing the probability of metastable events
when CLKA and CLKB operate asynchronously to one an-
other. ORA,
AEA
, IRA, and
AFA
are synchronized to CLKA.
ORB,
AEB
, IRB, and
AFB
are synchronized to CLKB. Tables
4 and 5 show the relationship of each port flag to FIFO1 and
FIF02.
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| IDT723632L15PF8 | 功能描述:IC FIFO SYNC 512X36X2 120QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723632L15PQF | 功能描述:IC FIFO SYNC 512X36X2 132QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數據速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723633L12PF | 功能描述:IC FIFO SYNC 512X36 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723633L12PF8 | 功能描述:IC FIFO SYNC 512X36 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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