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參數(shù)資料
| 型號： | IDT72125L50TP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 1K X 16 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 179K |
| 代理商： | IDT72125L50TP |
5.35
8
COMMERCIAL TEMPERATURE RANGES
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
Figure 9. Serial Read Expansion
OPERATING CONFIGURATIONS
Single Device Mode
The device must be reset before beginning operation so
that all flags are set to location zero. In the standalone case,
the RSIX line is tied HIGH and indicates single device opera-
tion to the device. The RSOX/
AEF
pin defaults to
AEF
and
outputs the Almost-Empty and Almost-Full Flag.
Width Expansion Mode
In the cascaded case, word widths of more than 16 bits can
be achieved by using more than one device. By tying the
RSOX and RSIX pins together, as shown in Figure 11, and
programming which is the Least Significant Device, a cas-
caded serial word is achieved. The Least Significant Device
is programmed by a LOW on the
FL
/DIR pin during reset. All
other devices should be programmed HIGH on the
FL
/DIR pin
at reset.
Figure 10. Single Device Configuration
2665 drw 13
SO
SOCP
RSOX/AEF
D
0–15
ALMOST-EMPTY/FULL FLAG
SERIAL DATA
PARALLEL DATA
RSIX
SERIAL OUTPUT CLOCK
Vcc
IN
OUT
2665 drw 12
FL/DIR
RS
SOCP
RSIX
RSOX
t
FLH
t
DIRS
15
0
t
FLS
t
DIRH
t
SOXD1
t
SOXD2
t
SIXS
t
RSIXPW
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