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| 型號： | IDT72125L50TP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 1K X 16 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 179K |
| 代理商： | IDT72125L50TP |
5.35
10
COMMERCIAL TEMPERATURE RANGES
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125
2665 drw 15
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #3
SO
W
D
0–15
FL/DIR
ADDRESS
DECODER
74FCT138
00
01
10
FULL
FLAG
HALF-FULL
FLAG
EMPTY
FLAG
HIGH AT RESET
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #2
SO
W
D
0–15
FL/DIR
HIGH AT RESET
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #1
SO
W
D
0–15
FL/DIR
LOW AT RESET
SERIAL OUTPUT CLOCK
SERIAL DATA
PARALLEL DATA
IN
OUT
NOTE:
1.
RS
= Reset Input,
FL
/FIR = First Load/Direction,
EF
= Empty Flag Output,
HF
= Half- Full Flag Output,
FF
= Full Flag Output.
2665 tbl 10
Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode
Inputs
FL
Internal Status
Outputs
Mode
RS
DIR
Read Pointer
Write Pointer
EF
HF
,
FF
Reset-First Device
Reset All Other Devices
Read/Write
0
0
1
0
1
X
X
X
0,1
Location Zero
Location Zero
X
Location Zero
Location Zero
X
0
0
X
1
1
X
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