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參數(shù)資料
| 型號(hào)： | IDT72125L50TP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 1K X 16 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大小： | 179K |
| 代理商： | IDT72125L50TP |
5.35
11
COMMERCIAL TEMPERATURE RANGE
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
2665 drw 16
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #6
SO
W
D
16–31
FL
/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #4
SO
W
D
16–31
FL
/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #2
SO
W
D
16–31
FL
/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #5
SO
W
D
0–15
FL
/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #3
SO
W
D
0–15
FL
/DIR
EF
RSIX
RSOX
HF
FF
SOCP
FIFO #1
SO
W
D
0–15
FL
/DIR
ADDRESS
DECODER
74FCT138
00
01
10
SERIAL OUTPUT CLOCK
LOW ON RESET
HIGH ON RESET
FULL
FLAG
HALF-FULL
FLAG
EMPTY
FLAG
SERIAL DATA
PARALLEL DATA
IN
OUT
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
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