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參數(shù)資料
| 型號(hào)： | IDT72125L50TP |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 |
| 中文描述： | 1K X 16 OTHER FIFO, 50 ns, PDIP28 |
| 封裝： | 0.300 INCH, THIN, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | IDT72125L50TP |
5.35
7
COMMERCIAL TEMPERATURE RANGE
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
2665 drw 09
SOCP
W
EF
t
REFSO
t
WEF
0
1
n–1
SO
DATA
IN
t
SOCEF
t
SOLZ
t
SOPD
NOTE 1
NOTE 2
2665 drw 11
SOCP
W
HF
t
WF
AEF
AEF
HALF-FULL (1/2)
HALF-FULL
7/8 FULL
7/8 FULL
ALMOST-EMPTY
(1/8 FULL – 1)
ALMOST-EMPTY
(1/8 FULL – 1)
t
WF
ALMOST-FULL (7/8 FULL + 1)
1/8 FULL
HALF-FULL + 1
t
SOCF
t
SOCF
Figure 8. Half-Full, Almost-Full and Almost-Empty Timings
NOTE:
1. Single Device Mode will not tri-state but will retain the last valid data.
Figure 7. Full Boundary Condition Timing
2665 drw 10
SOCP
W
FF
t
WPF
0
SO
DATA
IN
DATA
IN
VALID
DATA
OUT
VALID
1
n–1
t
SOCFF
t
WFF
t
DS
t
DH
t
SOPD
NOTE 1
NOTE 1
NOTE:
1. Once
EF
has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until
EF
goes HIGH.
2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.
Figure 6. Empty Boundary Condition Timing
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