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參數(shù)資料
| 型號： | IDT71V3579YSA75PFGI |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect |
| 中文描述： | 128K的米鼠36，256 × 18 3.3同步SRAM的3.3V的I / O的流量，通過輸出脈沖計數(shù)器，單周期取消 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 521K |
| 代理商： | IDT71V3579YSA75PFGI |
6.42
20
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and
TRST
.
Instruction Field
Value
Description
Revision Number (31:28)
0x2
Reserved for version number
IDT Device ID (27:12)
0x22C, 0x22E
Defines IDT part number 71V3577SA and 71V3579SA, respectively.
IDT JEDEC ID (11:1)
0x33
Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0)
1
Indicates the presence of an ID register
I5280 tbl 02
JTAG Identification Register Definitions (SA Version only)
Instruction
Description
OPCODE
EXTEST
Forces contents of the boundary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data fromdevice inputs
(2)
and outputs
(1)
to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
0001
DEVICE_ID
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
0010
HIGHZ
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
0011
RESERVED
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
0100
RESERVED
0101
RESERVED
0110
RESERVED
0111
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
1000
RESERVED
Same as above.
1001
RESERVED
1010
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
1101
RESERVED
Same as above.
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
1111
I5280 tbl 04
Available JTAG Instructions
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| IDT71V416L10BEG8 | 功能描述:IC SRAM 4MBIT 10NS 48FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤 |
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