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參數(shù)資料
| 型號(hào)： | IDT70V7519S200DR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 256K X 36 DUAL-PORT SRAM, 10 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 490K |
| 代理商： | IDT70V7519S200DR |
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IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CLK"A"
R/
W"A"
BANK ADDRESS
AND ADDRESS"A"
DATAIN"A"
CLK"B"
R/
W"B"
BANK ADDRESS
AND ADDRESS"B"
DATAOUT"B"
tSW
tHW
tSA
tHA
tSD
tHD
tSW
tHW
tSA
tHA
tCD2
Dn
An
Dn
5618 drw 10
tDC
tCO(3)
Timing Waveform of Port A Write to Pipelined Port B Read(1,2,4)
NOTES:
1.
CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2.
OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO
≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle
(ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
DATAIN "A"
CLK "B"
R/
W "B"
BANK ADDRESS
AND ADDRESS "A"
R/
W "A"
CLK "A"
BANK ADDRESS
AND ADDRESS "B"
An
Dn
tDC
DATAOUT "B"
5618 drw 11
Dn
tSW tHW
tSA
tHA
tSD
tHD
tHW
tCD1
tCO(3)
tDC
tSA
tSW
tHA
NOTES:
1.
CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2.
OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO
≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle
(i.e., time from write to valid read on opposite port will be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
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| IDT70V7519S200DRI | HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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| IDT70V9199L9PF | HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM |
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