參數(shù)資料
型號(hào)： IDT70V7519S200DR
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
中文描述： 256K X 36 DUAL-PORT SRAM, 10 ns, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 11/22頁(yè)
文件大?。?/td> 490K
代理商： IDT70V7519S200DR
6.42
IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
19
Functional Description
The IDT70V7519 is a high-speed 256Kx36 (9 Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
4Kx36banks.BasedonastandardSRAMcoreinsteadofatraditionaltrue
dual-port memory core, this bank-switchable device offers the benefits of
increased density and lower cost-per-bit while retaining many of the
featuresoftruedual-ports.Thesefeaturesincludesimultaneous,random
access to the shared array, separate clocks per port, 166 MHz operating
speed,full-boundarycounters,andpinoutscompatiblewiththeIDT70V3599
(128Kx36) dual-port family.
The two ports are permitted independent, simultaneous access into
separate banks within the shared array. Access by the ports into specific
banks are controlled by the bank address pins under the user's direct
control: each port can access any bank of memory with the shared array
that is not currently being accessed by the opposite port (i.e., BA0L - BA5L
≠BA0R-BA5R).Intheeventthatbothportstrytoaccessthesamebank
at the same time, neither access will be valid, and data at the two specific
addresses targeted by the ports within that bank may be corrupted (in the
case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
The IDT70V7519 provides a true synchronous Dual-Port Static RAM
5618 drw 20
IDT70V7519
CE0
CE1
CE0
CE1
BA6(1)
CE1
CE0
VDD
IDT70V7519
Control Inputs
BE,
R/
W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
Figure 4. Depth and Width Expansion with IDT70V7519
interface. Registered inputs provide minimal setup and hold times on
address, data and all critical control inputs.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operationoftheaddresscountersforfastinterleavedmemoryapplications.
A HIGH on
CE0 oraLOWonCE1 foroneclockcyclewillpowerdown
the internal circuitry on each port (individually controlled) to reduce static
power consumption. Dual chip enables allow easier banking of multiple
IDT70V7519s for depth expansion configurations. Two cycles are
required with
CE0 LOWandCE1 HIGHtoreadvaliddataontheoutputs.
Depth and Width Expansion
The IDT70V7519 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
TheIDT70V7519canalsobeusedinapplicationsrequiringexpanded
width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the
devices can be grouped as necessary to accommodate applications
needing 72-bits or wider.
NOTE:
1. In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are
controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently
being accessed by the opposite port (i.e., BA0L - BA6L
≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither
access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are
writing) or may result in invalid output (in the case that both ports are trying to read).
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