參數(shù)資料
型號: IDT70T653MS10BC
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
中文描述: 512K X 36 DUAL-PORT SRAM, 10 ns, PBGA256
封裝: BGA-256
文件頁數(shù): 1/24頁
文件大?。?/td> 309K
代理商: IDT70T653MS10BC
2003 Integrated Device Technology, Inc.
1
NOVEMBER 2003
DSC-5679/2
CE
0R
CE
1R
R/
W
R
BE
0R
BE
1R
BE
2R
BE
3R
512K x 36
MEMORY
ARRAY
Address
Decoder
A
18R
A
0R
Address
Decoder
CE
0L
CE
1L
R/
W
L
BE
0L
BE
1L
BE
2L
BE
3L
Dout0-8_L
DoDout0-8_R
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
B
E
3
R
B
E
2
R
B
E
1
R
B
E
0
R
I/O
0L-
I/O
35L
A
18L
A
0L
I/O
0R -
I/O
35R
Di n_L
ADDR_L
Di n_R
ADDR_R
OE
R
OE
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM
L
INT
L(1)
BUSY
L
R/
W
L
OE
L
R/
W
R
OE
R
CE
0L
CE
1L
CE
0R
CE
1R
BUSY
R
SEM
R
INT
R(1)
5679 drw 01
ZZ
CONTROL
LOGIC
ZZ
L(2)
JTAG
TCK
TMS
TRST
TDI
TDO
ZZ
R(2)
Functional Block Diagram
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Includes JTAG functionality
Available in a 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T653M easily expands data bus width to 72 bits or
more using the Busy Input when cascading more than one
device
Busy input for port contention management
Interrupt Flags
HIGH-SPEED 2.5V
512K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY
IDT70T653M
NOTES:
1.
INT
is non-tri-state totem-pole outputs (push-pull).
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INT
x and the sleep mode
pins themselves (ZZx) are not affected during sleep mode.
相關(guān)PDF資料
PDF描述
IDT70T653MS10BCI HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
IDT70T653MS12BC HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
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