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參數(shù)資料
| 型號： | IDT70T3539M |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 中文描述： | 高速與3.3V 2.5V的為512k × 36 SYNCHRONOU S雙，端口靜態(tài)RAM或2.5V的接口 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 421K |
| 代理商： | IDT70T3539M |
2004 Integrated Device Technology, Inc.
APRIL 2004
DSC 5678/5
1
Functional Block Diagram
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆
2.5V (±100mV) power supply for core
◆
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆
Includes JTAG functionality
◆
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
◆
Available in a 256-pin Ball Grid Array (BGA)
HIGH-SPEED 2.5V
512K x 36
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
PRELIMINARY
IDT70T3539M
REPEAT
R
ADS
R
A
0R
CNTEN
R
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
I/O
0R
- I/O
35R
Din_R
ADDR_R
OE
R
BE
3R
BE
2R
BE
1R
BE
0R
R/
W
R
CE
0R
CE
1R
1
0
1/0
FT
/PIPE
R
1a 0a
a
1b
0b
1c
0c
1d
0d
d
c
b
CLK
R
,
Address
Reg.
d c b a
0/1
0d 1d
0c 1c
0b 1b
0a 1a
B
W
2
R
B
W
1
R
B
W
0
R
FT
/PIPE
R
CReg.
CNTEN
L
ADS
L
REPEAT
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
B
W
0
L
B
W
1
L
B
W
2
L
B
W
3
L
I/O
0L
- I/O
35L
A
18L
A
0L
Din_L
ADDR_L
OE
L
5678 drw 01
BE
3L
BE
2L
BE
1L
BE
0L
R/
W
L
CE
0L
CE
1L
5ARRAY
CLK
L
a bcd
FT
/PIPE
L
0/1
1d 0d
1c 0c 1b 0b 1a 0a
B
W
3
R
,
JTAG
TCK
TMS
TRST
TDO
TDI
1
0
1/0
0d 1d
d
0c 1c
c
0b
1b
0a
1a
a
b
FT
/PIPE
L
1/0
1/0
INTERRUPT
COLLISION
DETECTION
LOGIC
R/
W
L
CE
0L
CE1L
R/
W
R
CE
0R
CE1R
INT
L
COL
L
INT
R
COL
R
ZZ
CONTROL
LOGIC
ZZ
L(1)
ZZ
R(1)
A
18R
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
◆
Selectable Pipelined or Flow-Through output mode
◆
Counter enable and repeat features
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Interrupt and Collision Detection Flags
◆
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
NOTE:
1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/
FT
x and OPTx and
the sleep mode pins themselves (ZZx) are not affected during sleep mode.
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| IDT70T3539MS166BC | HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
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