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參數(shù)資料
| 型號(hào)： | IDT29FCT520ATP |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 8-BIT, DSP-PIPELINE REGISTER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 92K |
| 代理商： | IDT29FCT520ATP |
6
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT29FCT520AT/BT/CT/DT
MULTILEVELPIPELINEREGISTER
Pulse
Generator
R T
D.U.T.
V CC
V IN
C L
V OUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
IN PU T
TIM IN G
IN PU T
ASYNCHRON OUS C ONTROL
PRES ET
CLEAR
ETC.
SYNC HRO N OU S CON TRO L
tSU
tH
tREM
tSU
tH
HIGH-LOW -HIGH
PULSE
LO W -H IGH -LOW
PULSE
tW
1.5V
SAM E PHASE
IN PU T TR ANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OU TPUT
OPPOSITE P HASE
IN PU T TR ANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CO NTR OL
IN PU T
3V
1.5V
0V
3.5V
0V
OU TPUT
NO RM A LLY
LO W
OU TPUT
NO RM A LLY
HIGH
SW ITC H
CLOSE D
SW ITC H
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENAB LE
DISA BLE
VOH
PRES ET
CLEAR
CLOC K ENABLE
ETC.
Octal lin k
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
8-link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT29FCT520ATPY | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT29FCT520ATQ | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT29FCT520ATSO | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT29FCT520B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:MULTILEVEL PIPELINE REGISTER |
| IDT29FCT520BD | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:MULTILEVEL PIPELINE REGISTER |
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