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參數(shù)資料
| 型號： | ICY7C1362C-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 20/31頁 |
| 文件大小： | 432K |
| 代理商： | ICY7C1362C-166BGI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 20 of 31
Thermal Resistance
[14]
Parameter
Θ
JA
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
100 TQFP
Package
29.41
119 BGA
Package
34.1
165 fBGA
Package
16.8
Unit
°C/W
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, per
EIA/JESD51.
Θ
JC
6.13
14.0
3
°C/W
Capacitance
[14]
Parameter
C
IN
C
CLK
C
I/O
Description
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V
V
DDQ
= 2.5V
100 TQFP
Package
5
5
5
119 BGA
Package
5
5
7
165 fBGA
Package
5
5
7
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Over the Operating Range
[17, 18]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
Notes:
17.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
18.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Description
250 MHz
Min.
1
200 MHz
Min.
1
166 MHz
Min.
1
Unit
ms
Max
Max
Max
V
DD
(Typical) to the First Access
[19]
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
1.8
1.8
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
2.8
3.0
3.5
ns
ns
1.25
1.25
1.25
OUTPUT
R = 317
R = 351
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.5V
3.3V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1 ns
≤
1 ns
(c)
OUTPUT
R = 1667
R =1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
T
= 1.25V
2.5V
ALL INPUT PULSES
V
DDQ
GND
90%
10%
90%
10%
≤
1 ns
≤
1 ns
(c)
3.3V I/O Test Load
2.5V I/O Test Load
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