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參數(shù)資料
| 型號： | ICY7C1362C-166BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/31頁 |
| 文件大小： | 432K |
| 代理商： | ICY7C1362C-166BGI |
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PRELIMINARY
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
CY7C1360C
CY7C1362C
Cypress Semiconductor Corporation
Document #: 38-05540 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 23, 2005
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 166 MHz
Registered inputs and outputs for pipelined operation
3.3V core power supply
2.5V/3.3V I/O operation
Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single Cycle Chip Deselect
Offered in Lead-Free 100-pin TQFP, 119-ball BGA and
165-Ball fBGA packages
TQFP Available with 3-Chip Enable and 2-Chip Enable
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode Option
Logic Block Diagram – CY7C1360C (256K x 36)
Functional Description
[1]
The CY7C1360C/CY7C1362C SRAM integrates 262,144 x 36
and 524,288 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
1
), depth-expansion Chip
Enables (CE
2
and
CE
3[2]
), Burst Control inputs (ADSC, ADSP,
and ADV), Write Enables (BW
X
, and BWE), and Global Write
(GW). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1360C/CY7C1362C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
is for A version of TQFP (3 Chip Enable option) and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
ARRAY
DQs
DQP
A
DQP
B
DQP
C
DQP
D
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
D
,DQP
D
BYTE
WRITE DRIVER
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| ICY7C1362C-166BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
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