參數(shù)資料
型號: ICSSSTV16857yL-T
英文描述: DDR 14-Bit Registered Buffer
中文描述: 復員14位注冊緩沖區(qū)
文件頁數(shù): 6/8頁
文件大?。?/td> 114K
代理商: ICSSSTV16857YL-T
6
ICSSSTV16857
Third party brands and names are the property of their respective owners.
Notes: 1. CL incluces probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DD
or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
10 MHz, Zo=50
, input
slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
TT
= V
REF
= V
DDQ
/2
6. V
IH
= V
REF
+ 310mV (ac voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS input.
7. V
IL
= V
REF
-310mV (ac voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. t
PLH
and t
PHL
are the same as t
pd
Test Point
Load Circuit
From Output
Under Test
C = 30 pF
(see Note 1)
V
TT
R =
LVCMOS
RESET#
Input
LVCMOS
RESET#
Input
V
/2
DD
t
inact
t
act
I
(see note 2)
DD
I
DDH
I
DDL
10%
90%
Voltage and Current Waveforms
Inputs Active and Inactive Times
Voltage Waveforms - Propagation Delay Times
Voltage Waveforms - Propagation Delay Times
Parameter Measurement Information (V
= 2.5V ±0.2V)
DD
Voltage Waveforms - Pulse Duration
Voltage Waveforms - Setup and Hold Times
V
/2
DD
V
DD
0 V
t
w
t
SU
t
h
V
IH
V
IH
V
OH
V
TT
V
TT
V
TT
V
OH
V
IH
V
IL
V
IL
V
OL
V
OL
V
I(pp)
V
I(pp)
V
IL
V
REF
V
REF
V
REF
V
REF
V
ICR
V
ICR
t
PHL
t
PHL
t
PHL
V
/2
DD
V
ICR
Input
Input
Timing
Input
Timing
Input
Output
Output
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