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參數(shù)資料
| 型號(hào)： | ICSSSTV16857yL-T |
| 英文描述： | DDR 14-Bit Registered Buffer |
| 中文描述： | 復(fù)員14位注冊(cè)緩沖區(qū) |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 114K |
| 代理商： | ICSSSTV16857YL-T |
Integrated
Circuit
Systems, Inc.
ICSSSTV16857
Third party brands and names are the property of their respective owners.
16857 Rev D 07/09/01
Pin Configuration
Recommended Application:
DDR Memory Modules
Product Features:
Differential clock signal
Meets SSTL_2 signal data
Supports SSTL_2 class I & II specifications
low-voltage operation
VDD = 2.3V to 2.7V
48 pin TSSOP package
DDR 14-Bit Registered Buffer
Truth Table
1
Block Diagram
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
CLK#
38
39
48
35
34
D1
VREF
RESET#
To 13 Other Channels
Q1
1
CLK
D1
R
Notes:
1.
H = High Signal Level
L = Low Signal Level
↑
= Transition LOW-to-HIGH
↓
= Transition HIGH -to LOW
X = Irrelevant
2.
Output level before the indicated
steady state input conditions were
established.
s
p
n
I
s
p
O
Q
Q
#
T
E
S
E
R
K
L
r
X
n
o
C
#
K
r
n
↓
↓
r
L
C
D
r
X
n
o
H
L
g
X
g
o
g
L
H
↑
↑
H
H
L
L
H
H
r
L
H
L
X
Q
0
)
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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