參數(shù)資料
型號: ICSSSTV16857yL-T
英文描述: DDR 14-Bit Registered Buffer
中文描述: 復(fù)員14位注冊緩沖區(qū)
文件頁數(shù): 2/8頁
文件大小: 114K
代理商: ICSSSTV16857YL-T
2
ICSSSTV16857
Third party brands and names are the property of their respective owners.
General Description
The 14-bit ICSSTV16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels
except for the RESET# input which is LVCMOS.
Pin Configuration
Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the
positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS
levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and
when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and
clock are switched off.
R
,
1
,
,
E
B
,
1
,
1
1
2
,
1
,
3
1
,
1
,
2
,
2
,
4
,
3
,
4
,
4
3
3
3
,
2
3
3
M
U
,
2
,
1
,
,
,
,
2
,
N
N
2
,
1
I
P
,
2
,
1
E
M
A
N
N
I
P
E
P
Y
T
N
O
I
T
P
I
R
C
S
E
D
,
)
1
Q
T
U
P
T
U
O
t
p
o
a
D
,
6
4
,
,
3
,
4
,
4
8
9
4
,
4
5
,
D
N
G
R
W
P
d
n
u
o
G
1
,
3
,
4
8
2
,
,
2
,
3
Q
D
D
V
R
W
P
e
g
a
v
y
p
u
t
p
O
4
)
1
D
T
U
P
N
I
t
p
n
a
D
K
K
D
D
E
S
E
R
L
L
C
C
V
E
V
T
T
U
U
R
U
U
P
P
W
P
P
N
N
P
N
N
I
I
t
p
p
n
a
v
w
o
e
e
n
n
k
k
c
c
o
o
e
y
p
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v
P
g
e
N
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C
t
R
t
p
n
#
t
e
g
)
a
v
v
u
5
#
T
F
R
T
T
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I
e
g
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