參數(shù)資料
型號: ICSSSTV16857yL-T
英文描述: DDR 14-Bit Registered Buffer
中文描述: 復(fù)員14位注冊緩沖區(qū)
文件頁數(shù): 5/8頁
文件大?。?/td> 114K
代理商: ICSSSTV16857YL-T
5
ICSSSTV16857
Third party brands and names are the property of their respective owners.
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD=2.5±0.2V
MIN
UNITS
TYP
133
2.4
3.1
1.5
0.018
MAX
200
2.8
5
4
f
clock
t
PD
t
RST
t
SL
Clock frequency
Clock to output time
Reset to output time
Output slew rate
Setup time, fast slew rate
2, 4
Setup time, slow slew rate
3, 4
Hold time, fast slew rate
2,4
Hold time, slow slew rate
3, 4
MHz
ns
ns
V/ns
ns
ns
ns
ns
1.1
1
Data before CK , CK#
0.75
0.9
0.75
0.9
t
SU
Data after CK , CK#
0.145
T
h
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate =1V/ns.
4 - CLK, CLK# signals input slew rates are =1V/ns.
3 - For data signal input slew rate =0.5V/ns and < 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
From
(Input)
f
clock
t
PD
CLK, CLK#
t
ph1
RESET#
To
VDD=2.5±0.2V
MIN
UNITS
(Output)
TYP
133
2.4
3.1
MAX
200
2.8
5
MHz
ns
ns
Q
Q
1.1
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