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參數(shù)資料
| 型號： | ICSSSTUB32871AHMLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | 32871 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5 X 11.50 MM, MO-205, TFBGA-96 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 199K |
| 代理商： | ICSSSTUB32871AHMLFT |
11
1186G—04/16/07
ICSSSTUB32871A
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN
MAX
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
V/ns
dV/dt_
Δ1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
VDD = 1.8V ± 0.1V
UNIT
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
VDDQ
MIN
TYP
MAX
UNITS
VOH
IOH = -8mA
1.7V
1.2
VOL
IOL = 8mA
1.7V
0.5
II
All Inputs
VI = VDD or GND
1.9V
±5
A
Standby (Static)
RESET = GND
200
A
Operating (Static)
VI = VIH(AC) or VIL(AC),
RESET = VDD
150
mA
Dynamic operating
(clock only)
RESET = VDD,VI = VIH(AC)
or VIL(AC), CLK and CLK
switching 50% duty cycle.
TBD
A/clock
MHz
Dynamic Operating
(per each data
input)
RESET = VDD, VI = VIH(AC)
or VIL (AC), CLK and CLK
switching 50% duty cycle.
One data input switching
at half clock frequency,
50% duty cycle
TBD
A/ clock
MHz/data
Data Inputs
2.5
5
CLK and CLK
2
3.8
RESET
4.5
pF
Notes:
1 - Guaranteed by design, not 100% tested in production.
Ci
VI = VDDQ or GND
IDD
IDDD
IO = 0
CONDITIONS
VI = VREF ±350mV
VICR = 1.25V, VI(PP) = 360mV
pF
V
1.8V
1.9V
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