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參數(shù)資料
| 型號： | ICSSSTUB32871AHMLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | 32871 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5 X 11.50 MM, MO-205, TFBGA-96 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 199K |
| 代理商： | ICSSSTUB32871AHMLFT |
7
1186G—04/16/07
ICSSSTUB32871A
Register Timing
CK
Dn (1)
Qn
tsu
CK
n
n + 1
n + 2
n + 3
n + 4
DCSn
RESET
tACT
th
tPDM, tPDMSS
CK to Q
PARIN
tsu
th
tPHL, tPLH
CK to PTYERR
tPHL
CK to PTYERR
PTYERR
H, L, or X
H or L
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a
minimum time of t
(max) to avoid false error.
ACT
Figure 4
RESET switches from L to H
—
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