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參數(shù)資料
| 型號： | ICSSSTUB32871AHMLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | 32871 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5 X 11.50 MM, MO-205, TFBGA-96 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大小： | 199K |
| 代理商： | ICSSSTUB32871AHMLFT |
8
1186G—04/16/07
ICSSSTUB32871A
Register Timing
Figure 5 — RESET being held HIGH
CK
Dn (1)
Qn
tsu
002aaa984
CK
n
n + 1
n + 2
n + 3
n + 4
DCSn
RESET
th
tPDM, tPDMSS
CK to Q
PARIN
th
tPHL, tPLH
CK to PTYERR
PTYERR
Output signal is dependent on the pr
ior unknown event
H or L
Unknown input event
tsu
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| ICSSSTUF32864AYH-T | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICSSSTUB32871AZLFT | 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32871AZT | 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32872A | 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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