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參數(shù)資料
| 型號(hào)： | ICS951402YFLF-T |
| 英文描述： | Programmable Timing Control Hub for P4 processor |
| 中文描述： | 可編程定時(shí)控制中心的P4處理器 |
| 文件頁數(shù)： | 1/23頁 |
| 文件大小： | 303K |
| 代理商： | ICS951402YFLF-T |
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
Block Diagram
Pin Configuration
VDDREF 1
FS0/REF0 2
FS1/REF1 3
FS2/REF2 4
GNDREF 5
X1 6
X2 7
GND 8
VDD 9
*VttPWR_GD/PD# 10
PCI66/33#_SEL 11
PCI_STOP#* 12
VDDPCI 13
FS3/PCICLK_F0 14
FS4/PCICLK_F1 15
PCICLK0 16
PCICLK1 17
GNDPCI 18
VDDPCI 19
PCICLK2 20
PCICLK3 21
PCICLK4 22
PCICLK5 23
GNDPCI 24
Recommended Application:
ATI chipset, P4 system, Banias system
Output Features:
2 - Pairs of differential CPUCLKs (differential current mode)
1 - SDRAM @ 3.3V
8 - PCI @3.3V (selectable 33/66 MHz) (2 free-running)
2 - AGP @ 3.3V
2- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
2
C
(Default is 24MHz)
3- REF @3.3V, 14.318MHz.
Features/Benefits:
Support for Intel Banias power management features
Programmable output frequency, divider ratios, output rise/
falltime, output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
Supports spread spectrum for EMI reduction; default is
spread spectrum ON.
Programmable Timing Control Hub for P
4
processor
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
48-Pin TSSOP & SSOP
Power Groups
VDDCPU = CPU
VDDPCI = PCICLK_F, PCICLK
VDDSD = SDRAM
AVDD48 = 48MHz, 24MHz, fixed PLL
AVDD = Analog Core PLL
VDDAGP= AGP
VDDREF = Xtal, REF
Skew Requirements
48 VDDSDR
47 SDRAM_OUT
46 GNDSDR
45 CPU_STOP#*
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 GNDCPU
40 CPUCLKT0
39 CPUCLKC0
38 IREF
37 GND
36 AVDD
35 SCLK
34 SDATA
33 GNDAGP
32 AGPCLK0
31 AGPCLK1
30 VDDAGP
29 AVDD48
28 48MHz_0
27 48MHz_1
26 24_48MHz/SEL24_48#MHz**
25 GND48
I
PCI-PCI
AGP-AGP
CPU-AGP
CPU-PCI
<±350ps
<±350ps
<±500ps
<±500ps
<±1ns
CPU-SDRAM
<±1ns
AGP-PCI
AGP leading
I REF
CPU
DIVDER
PLL2
PLL1
Spread
Spectrum
48MHz (0:1)
24_48MHz
PCICLK (5:0)
AGP (1:0)
PCICLK_F (1:0)
2
2
1
6
3
X1
X2
XTAL
OSC
SDRAM
SDRAM_OUT
PCI
DIVDER
Stop
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
PD#/Vtt_PWRGD
PCI66/33#SEL
24_48SEL#
Control
Logic
Config.
Reg.
/ 2
REF (2:0)
AGP
DIVDER
Stop
2
2
CPUCLKT (1:0)
CPUCLKC (1:0)
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