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參數(shù)資料
| 型號： | ICS951402YFLF-T |
| 英文描述： | Programmable Timing Control Hub for P4 processor |
| 中文描述： | 可編程定時(shí)控制中心的P4處理器 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICS951402YFLF-T |
16
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
V
DD
+0.3
UNITS
Input High Voltage
V
IH
2
V
Input Low Voltage
V
IL
V
SS
-
0.3
-5
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
mA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5
mA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
C
L
= Full load; Select @ 100
MHz
C
L
=Full load; Select @ 133
MHz
IREF=5 mA
V
DD
= 3.3 V
-200
Operating Supply Current
I
DD3.3OP
229
230
360
mA
I
DD3.3OP
220
233
360
mA
Powerdown Current
Input Frequency
Pin Inductance
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
38.1
14.32
45
mA
MHz
nH
pF
pF
pF
7
5
6
Logic Inputs
Output pin capacitance
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
27
36
45
Clk Stabilization
1,2
T
STAB
1
1.8
ms
t
PZH
,t
PZL
Output enable delay (all outputs)
1
10
ns
t
PHZ
,t
PLZ
Output disable delay (all outputs)
1
10
ns
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for buffered and un-buffered timing requirements.
Delay
1
Input Capacitance
1
Input Low Current
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