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參數(shù)資料
| 型號： | ICS951402YFLF-T |
| 英文描述： | Programmable Timing Control Hub for P4 processor |
| 中文描述： | 可編程定時控制中心的P4處理器 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ICS951402YFLF-T |
7
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table
: Reserved Register
Byte 3
Pin #
Name
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
I
2
C Table
: Functionality and Frequency Select Register
Byte 4
Pin #
Name
Bit 7
-
FS3
Bit 6
-
FS2
Bit 5
-
FS1
Bit 4
-
FS0
Control
Function
Freq Select Bit 7
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Frequency H/W or
IIC Select
Freq Select Bit 2
SPREAD Enable
Output Control
Type
0
1
PWD
RW
RW
RW
RW
0
0
0
0
See
Frequency Table
Bit 3
-
FS Source
RW
Latch Input
IIC
0
Bit 2
Bit 1
Bit 0
Note:
If Byte4 bit1 = 0 then FS4=0
I
Byte 5
Pin #
-
-
-
FS4
SS_EN
All Outputs
RW
RW
RW
See Frequency Table
OFF
Normal
0
1
0
ON
Tri-state
2
C Table
: Output Control and Read Back Register
Name
Control
Function
Output Control
Output Control
24 or 48 Select
FS4 Read back
FS3 Read back
FS2 Read back
FS1 Read back
FS0 Read back
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
31
32
26
-
-
-
-
-
AGP1
AGP0
24_48#SEL
FS4RB
FS3RB
FS2RB
FS1RB
FS0RB
RW
RW
RW
R
R
R
R
R
Disable
Disable
48MHz
-
-
-
-
-
Enable
Enable
24MHz
-
-
-
-
-
1
1
X
X
X
X
X
X
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