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參數(shù)資料
| 型號(hào)： | ICS951402YFLF-T |
| 英文描述： | Programmable Timing Control Hub for P4 processor |
| 中文描述： | 可編程定時(shí)控制中心的P4處理器 |
| 文件頁(yè)數(shù)： | 21/23頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | ICS951402YFLF-T |
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21
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICS951402YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 processor |
| ICS951403 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951403YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951403YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951411 | 制造商:ICS 制造商全稱:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
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