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參數(shù)資料
| 型號： | ICS950818 |
| 英文描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 中文描述： | 頻率發(fā)生器200MHz的CPU的時鐘差分 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | ICS950818 |
5
ICS950818
0825F—11/19/03
Pin #
-
Name
0
1
PWD
0
Bit 7
Spread Enabled
Spread Spectrum Control
Power down mode output level
0= CPU driven in power down
1= undriven
VCH/66.66 Select
Reflects value of pin
Reflects value of pin at power up.
Also can be set.
(Reserved)
Frequency Selection
Frequency Selection
RW
OFF
ON
Bit 6
-
CPUCLKT(1:0)
RW
x2 IREF
Hi-Z
0
Bit 5
Bit 4
31
44
3V66_1/VCH_CLK
CPU_STOP#
RW
R
66.66
Stop
48.00
Active
0
X
Bit 3
30
PCI_STOP#
RW
Stop
Active
X
Bit 2
Bit 1
Bit 0
Note:
-
-
R
R
R
-
-
-
-
-
-
X
X
X
46
36
FS1
FS0
Pin #
-
Name
-
0
-
1
-
PWD
X
Bit 7
(Reserved)
R
Bit 6
-
CPUCLKT(1:0)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
Allow control of output with
assertion of CPU_STOP#.
Allow control of output with
assertion of CPU_STOP#.
(Reserved)
Output control
Output control
(Reserved)
RW
x2 IREF
Hi-Z
0
Bit 5
39, 38
CPUCLKT1, CPUCLKC1
(see note)
CPUCLKT0, CPUCLKC0
(see note)
-
CPUCLKT1, CPUCLKC1
CPUCLKT0, CPUCLKC0
-
CPUCLK(1:0) can be turned on/off by CPU_STOP#. Refer to table 3.
RW
Not
Freerun
Not
Freerun
-
Disable
Disable
-
Freerun
0
Bit 4
43, 42
RW
Freerun
0
Bit 3
Bit 2
Bit 1
Bit 0
Note:
-
R
-
X
1
1
X
39, 38
43, 42
-
RW
RW
R
Enable
Enable
-
Pin #
47
14
13
12
-
10
9
8
PCICLK(5:0) can be turned on/off by PCI_STOP#. Refer to table 2.
Name
REF
PCICLK5
PCICLK4
*PCICLK3
-
*PCICLK2
PCICLK1
PCICLK0
0
1
PWD
0
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
1X or 0.5X Strength control
Output control
Output control
Output control
Reserved
Output control
Output control
Output control
RW
RW
RW
RW
X
RW
RW
RW
1X
0.5X
Enable
Enable
Enable
-
Enable
Enable
Enable
Disable
Disable
Disable
-
Disable
Disable
Disable
Control Function
Affected Pin
Bit Control
Control Function
Affected Pin
For PCI_STOP# function, refer to table 2.
Type
Bit Control
Type
BYTE
0
BYTE
1
BYTE
2
Control Function
Bit Control
Affected Pin
Type
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