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參數(shù)資料
| 型號(hào)： | ICS950812YFLFT |
| 英文描述： | LED STANDARD GREEN 3MM T-1 |
| 中文描述： | 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分 |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 225K |
| 代理商： | ICS950812YFLFT |
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ICS950812
0542G—08/21/03
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch
low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next
rising edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2
C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition. When the I
2
C Bit 6 of Byte 1 is programmed to '0'
the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive
current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not
be driven . When the I
2
C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU
and CPU# outputs will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#
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0
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CPU_STOP#
CPUCLKT
CPUCLKC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS950812YGLFT | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950813 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950813YFT | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950813YGT | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
| ICS950818 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks |
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