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參數(shù)資料
| 型號： | ICS950813YGT |
| 英文描述： | Frequency Generator with 200MHz Differential CPU Clocks |
| 中文描述： | 頻率發(fā)生器200MHz的CPU的時鐘差分 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大小： | 265K |
| 代理商： | ICS950813YGT |
Integrated
Circuit
Systems, Inc.
ICS950813
Advance Information
0708—10/10/02
Block Diagram
Recommended Application:
CK-408 clock for Brookdale/Odem/Montara-GM for P4/Banias
processor.
Output Features:
3 Differential CPU Clock Pairs @ 3.3V
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Provides standard frequencies and additional 3%, 5%
and 10% over-clocked frequencies
Supports spread spectrum modulation:
No spread, Center Spread (±0.3%, ±0.55%), or Down
Spread (-0.5%, -0.75%)
Offers adjustable PCI early clock via latch inputs
Selectable 1X or 2X strength for REF via I
2
C interface
Programmable group to group skew
Linear programmable frequency and spreading %
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through
I
2
C interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Pin Configuration
Frequency Generator with 200MHz Differential CPU Clocks
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
VDDREF
1
2
3
4
5
6
7
8
9
56 REF
55 FS1
54 FS0
53 CPU_STOP#*
52 CPUCLKT0
51CPUCLKC0
50 VDDCPU
49 CPUCLKT1
48 CPUCLKC1
47 GND
46 VDDCPU
45 CPUCLKT2
44 CPUCLKC2
43 MULTSEL*
42 IREF
41 GND
40 PWRSAVE#*
39 48MHz_USB/FS2
**
38 48MHz_DOT
37 VDD48
36 GND
35 3V66_1/VCH_CLK/FS3
**
34 PCI_STOP#*
33 3V66_0/FS4
**
32 VDD3V66
31 GND
30 SCLK
29 SDATA
X1
X2
GND
PCICLK_F0
PCICLK_F1
*ASEL/PCICLK_F2
VDDPCI
GND
PCICLK0 10
**E_PCICLK1/PCICLK1 11
PCICLK2 12
**E_PCICLK3/PCICLK3 13
VDDPCI 14
GND 15
PCICLK4 16
PCICLK5 17
PCICLK6 18
VDD3V66 19
GND 20
3V66_2 21
3V66_3 22
3V66_4 23
3V66_5 24
*PD# 25
VDDA 26
GND 27
Vtt_PWRGD# 28
56-Pin 300mil SSOP
56-Pin 240mil TSSOP
*
These inputs have 120K internal pull-up resistors to VDD.
**
Internal pull-down resistors to ground.
I
Functionality Table
CPU
MHz
100.00
133.33
200.00
166.66
AGP
MHz
66.67
66.67
66.67
66.66
PCI
MHz
33.33
33.33
33.33
33.33
0
0
1
1
0
1
0
1
FS1
FS0
PLL2
PLL1
Spread
Spectrum
3V66 (5:2)
48MHz_USB
48MHz_DOT
X1
X2
XTAL
OSC
3V66
DIVDER
PD#
Vtt_PWRGD#
PWRSAVE#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (4:0)
SDATA
SCLK
I REF
Control
Logic
Config.
Reg.
REF
CPUCLKT (2:0)
CPUCLKC (2:0)
3V66_0
CPU
DIVDER
3
3
Stop
3V66_1/VCH_CLK
PCICLK (6:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
Asynchronous AGP/PCI Frequency Selection Table
Byte7 Bit5 Byte7 Bit4
AGP Frequency
0
0
0
1
1
0
1
1
PCI Frequency
33.00
37.72
44.00
--
66.00
75.43
88.00
--
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