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參數(shù)資料
| 型號： | ICS9248YF-135-T |
| 元件分類： | XO, clock |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 191K |
| 代理商： | ICS9248YF-135-T |
3
ICS9248-135
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2C serial interface information
The information in this section assumes familiarity with I
2C programming.
For more information, contact ICS for an I
2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
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PDF描述 |
|---|---|
| ICS9248YF-80 | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9248YF-99 | 150.29 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YF-138 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-141-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ System Clock Chip |
| ICS9248YF-146-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-157-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-163-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ System Clock Chip |
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