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參數(shù)資料
| 型號： | ICS9248YF-135-T |
| 元件分類： | XO, clock |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 191K |
| 代理商： | ICS9248YF-135-T |
7
ICS9248-135
Third party brands and names are the property of their respective owners.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-135. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-135.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
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| ICS9248YF-80 | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YF-138 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-141-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ System Clock Chip |
| ICS9248YF-146-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-157-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-163-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ System Clock Chip |
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