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參數(shù)資料
| 型號(hào)： | ICS9248YF-135-T |
| 元件分類： | XO, clock |
| 英文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁(yè)數(shù)： | 8/15頁(yè) |
| 文件大小： | 191K |
| 代理商： | ICS9248YF-135-T |
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ICS9248-135
Third party brands and names are the property of their respective owners.
The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2C interface allows changing functions, stop clock programming and frequency selection.
General Description
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 6, 15, 19, 27,
30, 36, 42
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
REF0
OUT
14.318 MHz reference clock.
FS3
IN
Frequency select pin.
3, 10, 16, 22, 33,
39, 44
GND
PWR
Ground pin for 3V outputs.
4
X1
IN
Crystal input,nominally 14.318MHz.
5
X2
OUT
Crystal output, nominally 14.318MHz.
FS1
IN
Frequency select pin.
PCICLK_F
OUT
Free running PCICLK clock output. Not affected by PCI_STOP#
FS2
IN
Frequency select pin.
PCICLK1
OUT
PCI clock outputs.
14, 13, 12, 11, 9
PCICLK (6:2)
OUT
PCI clock outputs.
17
SDRAM_STOP#
IN
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low
18
PD#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
20
CPU_STOP#
IN
Stops all CPUCLKs clocks at logic 0 level, when input low
21
PCI_STOP#
IN
Stops all PCICLKs clocks at logic 0 level, when input low
38, 37, 35, 34,
32, 31, 29, 28
SDRAM (7:0)
OUT
SDRAM clock outputs
23
SDATA
IN
Data input for I
2C serial input, 5V tolerant input
24
SCLK
IN
Clock input of I
2C input, 5V tolerant input
CPU2.5_3.3#
IN
Voltage select 2.5V when high - 3.3V when low
24_48MHz
OUT
Clock output for super I/O/USB default is 24MHz
FS0
IN
Frequency select pin.
48MHz
OUT
48MHz output clock
41, 40
SDRAM_F (1:0)
OUT
Free running SDRAM clock outputs. Not affected by SDRAM_STOP#
45, 43
CPUCLK (1:2)
OUT
CPU clock outputs.
46
CPUCLK_F
OUT
Free running CPUCLK clock output. Not affected by CPU_STOP#
47
VDDLCPU
PWR
Power pin for the CPUCLKs. 2.5V
48
REF1
OUT
14.318 MHz reference clock.
26
2
7
8
25
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9248YF-80 | 133.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| ICS9248YF-99 | 150.29 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ID09S33E4GV00 | 9 CONTACT(S), FEMALE, D SUBMINIATURE CONNECTOR, SOLDER |
| ID09S33E4GI00LF | 9 CONTACT(S), FEMALE, D SUBMINIATURE CONNECTOR, SOLDER |
| ID09S33E4GI00 | 9 CONTACT(S), FEMALE, D SUBMINIATURE CONNECTOR, SOLDER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YF-138 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-141-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ System Clock Chip |
| ICS9248YF-146-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-157-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YF-163-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ System Clock Chip |
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