參數資料
型號: ICS853S012AKI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 853S SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封裝: 5 MM X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32
文件頁數: 17/17頁
文件大?。?/td> 2291K
代理商: ICS853S012AKI
IDT / ICS LVPECL CLOCK/DATA MULTIPLEXER
9
ICS853S012AKI REV. A JANUARY 4, 2007
ICS853S012I
12:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK/DATA MULTIPLEXER
PRELIMINARY
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
A
3.3V LVPECL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
A
BUILT-IN PULLUP CML DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
A
3.3V LVDS DRIVER WITH AC COUPLE
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both V
SWING and VOH must meet the VPP and VCMR
input requirements.
Figures 2A to 2F show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
AN
IDT OPEN COLLECTOR CML DRIVER
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
AN
SSTL DRIVER
FIGURE 2F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
BY A
3.3V LVDS DRIVERER
R3
125
3.3V
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R4
125
LVPECL
R2
84
3.3V
R1
84
Zo = 50 Ohm
3.3V
HiPerClockS
CLK
nCLK
3.3V
3. 3V
3.3V
R1
50
CML
Zo = 50 Ohm
R2
50
Z o = 50 Ohm
R6
100 - 200
R5
100 - 200
C2
C1
3.3V
R3
84
R2
125
3.3V
3.3V LVPEC L
HiPerClock S
CLK
nCLK
3.3V
R1
125
R4
84
CML Built-In Pull-Up
Zo = 50 Ohm
3.3V
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
HiPerClockS
CLK
nCLK
R2
120
R4
120
2.5V
Zo = 60 Ohm
R1
120
2.5V
R3
120
Zo = 60 Ohm
SSTL
CML Built-In Pull-Up
Zo = 50 Ohm
3. 3V
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
相關PDF資料
PDF描述
ICS853S202AYI 853S SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
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