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參數(shù)資料
| 型號： | ICS5342 |
| 英文描述： | 16-Bit Integrated Clock-LUT-DAC |
| 中文描述： | 16位集成的時鐘- LUT的發(fā)展援助委員會 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大小： | 1017K |
| 代理商： | ICS5342 |
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ICS5342
GENDAC
14
Functional Description
This section describes the register address and bit definition
for the RAMDAC and the Frequency Synthesizer sections.
Color Palette
Command Register
(RS0-RS2 = 011)
(RS0-RS1 = 01 with hidden flag)
By setting bits 4 and 7-5 in the command register the
ICS5342 can be programmed for different color modes and
the DACs can be turned off for low power operation.
Bit 7-4
Color Mode Select - These three bits select the
Color Mode of RAMDAC operation as shown in
the following table “Color Mode Select” (default
is 0 at power up).
Bit 3-2
(Reserved) Set to ‘0’ for future compatibility.
Bit 1
Test Mode - When bit 1 is set checksum accumu-
lation is enabled. If bit 0 is also set the oscillator
and synthesizers are turned off for minimum
noise.
Bit 0
Power Down Mode of RAMDAC - When this bit
is set to 0 (default is 0), the device operates nor-
mally. If this bit is set to 1, the power and clock
to the Color Palette RAM and DACs are turned
off. The data in the Color Palette RAM are still
preserved. The CPU can access without loss of
data by internal automatic clock start/stop con-
trol. The DAC outputs become the same as
BLANK* (sync) level output during power down
mode. This bit does not affect the PLL clock syn-
thesizer function unless test mode is enabled.
Command Registers
7654
3
2
1
0
2103
Reserved = 0
Test mode
Snooze
Color Mode Select
8-BIT INTERFACE
Mode
Number
CM3
(CR4)
CM2
(CR7)
CM1
(CR6)
CM0
(CR5)
Color Mode
Clock Cycles/
Pixel Bits
0
0000
8-bit Pseudo Color With Palette (default)
1
0001
15-bit Direct Color With Bypass (Hi-Color)
2
3
0010
24-Bit True Color With Bypass (True Color)
3
2
0011
16-bit Direct Color With Bypass (XGA)
2
1
0100
15-bit Direct Color With Bypass (hi-color)
2
1
0101
15-bit Direct Color With Bypass (Hi-Color)
2
0110
15-bit Direct Color With Bypass (Hi-Color)
2
3
0111
24-bit True Color With Bypass (True Color)
3
16-BIT INTERFACE
Mode
Number
CM3
(CR4)
CM2
(CR7)
CM1
(CR6)
CM0
(CR5)
Color Mode
Clock Cycles/
Pixel Bits
4
1000
Multiplexed 16-bit Pseudo Color With Palette
1/2
5
1001
15-bit Direct Color With Bypass (Hi-Color)
1
6
1010
16-bit Direct Color With Bypass (XGA
1
7
1011
24-bit True Color With Bypass (True Color)
2
8
1100
24-bit Packed True Color With Bypass
(true-color)
3/2
1101
Reserved
1110
Reserved
1111
Reserved
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|---|---|
| IC42S81600 | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS5342-1 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342-2 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342-3 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342ADD | 制造商:ICS 制造商全稱:ICS 功能描述:Addendum to ICS5342 Data Sheet |
| ICS5342V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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