參數(shù)資料
型號: ICS5342
英文描述: 16-Bit Integrated Clock-LUT-DAC
中文描述: 16位集成的時鐘- LUT的發(fā)展援助委員會
文件頁數(shù): 34/36頁
文件大?。?/td> 1017K
代理商: ICS5342
ICS5342
GENDAC
7
* Characterized values only
DAC Characteristics
Parameter
Symbol
Min
Max
Units
Test Conditions
Maximum output voltage
Vo (max)
1.5
V
Io ≤ 10 mA
Maximum output current
Io (max)
21
mA
Vo ≤ 1V
Full scale error
± 5
%
note A, B
DAC to DAC correlation
±2
%
note B
Integral Linearity, 6-bit
±0.5
LSB
note B
Integral Linearity, 8-bit
±1
LSB
note B
Full scale settling time*, 6-bit
28
ns
note C
Full scale settling time*, 8-bit
20
ns
note C
Rise time (10% to 90%)*
6
ns
note C
Glitch energy*
200
pV.s
note C
PLL AC Characteristics
Parameter
Symbol
Min
Max
Units
Test Conditions
Clock 0 operating range
f0
25
135
MHz
Clock 1 operating range
f1
25
135
MHz
Output clocks rise time*
tr
3
ns
25 pF load, TTL levels
Output clocks fall time*
tr
3
ns
25 pF load, TTL levels
Duty Cycle*
dt
40/60
60/40
%
Jitter, one sigma*
j1s
130 ps
ps
Jitter, absolute*
jabs
-300 ps
300 ps
ps
Input reference frequency*
fref
5
25
MHz
Typically 14.318 MHz
AC Electrical Characteristics (note: J)
Parameter
Symbol
80 MHZ
110MHz
135Mhz
Units
Test
Conditions
Min
Max
Min
Max
Min
Max
PCLK period
tCHCH
12.5
9.09
7.4
ns
PCLK jitter
t
CHCH*
±2.5
+2.5
%
note D
PCLK width low
tCLCH
5
3.6
3
ns
PCLK width high
tCHCL
5
3.6
3
ns
Pixel word setup time
tPVCH
332ns
note E
Pixel word hold time
tCHPX
321ns
note E
BLANK* setup time
tBVCH
332ns
note E
BLANK* hold time
tCHBX
321ns
note E
PCLK to valid DAC
output
tCHAV*
20
ns
note F
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