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參數(shù)資料
| 型號： | ICS5342 |
| 英文描述： | 16-Bit Integrated Clock-LUT-DAC |
| 中文描述： | 16位集成的時鐘- LUT的發(fā)展援助委員會 |
| 文件頁數(shù)： | 36/36頁 |
| 文件大?。?/td> | 1017K |
| 代理商： | ICS5342 |
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ICS5342
GENDAC
9
* Characterized values only
XIN input clock fall
time
tXCLKF*
15
ns
TTL levels
AC Electrical Characteristics (note: J)
Parameter
Symbol
80 MHZ
110MHz
135Mhz
Units
Test
Conditions
Min
Max
Min
Max
Min
Max
Notes:
A. Full scale error is derived from design equation:
{[(F.S.IOUT)RL – 2.1(IREF)RL] / [2.1(IREF)RL]} 100%
VBLACK LEVEL= 0 V
F.S.IOUT = Actual full scale measured output
B. R= 37.5
, I
REF = – 8.88 mA
C. ZI = 37.5 + 30 pF, IREF = – 8.88 mA
D. This parameter is the allowed Pixel Clock frequency
variation. It does not permit the Pixel Clock period to
vary outside the minimum values for Pixel Clock
(tCHCH) period.
E.
The color palette’s pixel address is required to be a valid
logic level with the appropriate setup and hold times at
each rising edge of PCLK (this requirement includes the
blanking period).
F.
The output delay is measured from the 50% point of the
rising edge of CLOCK to the valid analog output. A
valid analog output is dened when the analog signal is
halfway between its successive values.
G. This applies to different analog outputs on the same
device.
H. Measured at
± 200 mV from steady state output voltage.
I.
This parameter allows synchronization between opera-
tions on the microprocessor interface and the pixel
stream being processed by the color palette.
J.
The following specications apply for VDD = +5V±
0.5V, GND=0. Operating Temperature = 0C to 70C.
K. Except for SENSE pin.
AC Test Conditions
Input pulse levels...................................................VDD to 3V
Input rise and fall times (10% to 90%) ............................ 3 ns
Digital input timing reference level ............................... 1.5 V
Digital output timing reference level .............0.8 V and 2.4 V
Capacitance
C1 Digital input............................................................... 7 pF
C0 Digital output............................................................. 7 pF
C0A Analog output ........................................................ 10 pF
Clock Load
General Operation
The ICS5342 GENDAC is intended for use as the analog out-
put stage of raster scan video systems. It contains a high-
speed Random Access Memory of 256 x 18-bit words, three
6/8-bit high-speed DACs, a microprocessor/graphic control-
ler interface, a pixel word mask, on-chip comparators, and
two user programmable frequency generators.
An externally generated BLANK* signal can be applied to
pin 7 of the ICS5342. This signal acts on all three of the ana-
log outputs. The BLANK* signal is delayed internally so that
it appears with the correct relationship to the pixel bit stream
at the analog outputs.
A pixel word mask is included to allow the incoming pixel
address to be masked. This permits rapid changes to the effec-
CLK
25 pF
1.4V
200
5342_03
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS5342-1 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342-2 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342-3 | 制造商:ICS 制造商全稱:ICS 功能描述:Analog IC |
| ICS5342ADD | 制造商:ICS 制造商全稱:ICS 功能描述:Addendum to ICS5342 Data Sheet |
| ICS5342V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
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