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| 型號(hào)： | AM79C972BKIW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| 中文描述： | 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 113/130頁(yè) |
| 文件大?。?/td> | 1580K |
| 代理商： | AM79C972BKIW |
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Am79C972
113
Writing a 1 to UNIT will clear
UNITCMD and stop interrupts.
Read/Write accessible always.
UINTCMD
is
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
6
UINT
User Interrupt. UINT is set by the
Am79C972 controller after the
host has issued a user interrupt
command by setting UINTCMD
(CSR4, bit 7) to 1.
Read/Write accessible always.
UINT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect.
UINT
is
H_RESET or S_RESET or by
setting the STOP bit.
cleared
by
5
RCVCCO
Receive Collision Counter Over-
flow is set by the Am79C972 con-
troller when the Receive Collision
Counter (CSR114 and CSR115)
has wrapped around.
When RCVCCO is set, INTA is
asserted if IENA is 1 and the
mask bit RCVCCOM is 0.
Read/Write accessible always.
RCVCCO is cleared by the host
by writing a 1. Writing a 0 has no
effect. RCVCCO is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
4
RCVCCOM Receive Collision Counter Over-
flow Mask. If RCVCCOM is set,
the RCVCCO bit will be masked
and unable to set the INTR bit.
Read/Write accessible always.
RCVCCOM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
3
TXSTRT
Transmit Start status is set by the
Am79C972 controller whenever it
begins transmission of a frame.
When TXSTRT is set, INTA is as-
serted if IENA is 1 and the mask
bit TXSTRTM is 0.
Read/Write accessible always.
TXSTRT is cleared by the host by
writing a 1. Writing a 0 has no ef-
fect. TXSTRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
2
TXSTRTM
Transmit Start Mask. If TX-
STRTM is set, the TXSTRT bit
will be masked and unable to set
the INTR bit.
Read/Write accessible always.
TXSTRTM is set to 1 by
H_RESET or S_RESET and is
not affected by the STOP bit.
1-0
RES
Reserved locations. Written as
zeros and read as undefined.
CSR5: Extended Control and Interrupt 1
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR5 and write back
the value just read to clear the interrupt condition.
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
TOKINTD
Transmit OK Interrupt Disable. If
TOKINTD is set to 1, the TINT bit
in CSR0 will not be set when a
transmission was successful.
Only a transmit error will set the
TINT bit.
TOKINTD has no effect when
LTINTEN (CSR5, bit 14) is set to
1. A transmit descriptor with
LTINT set to 1 will always cause
TINT to be set to 1, independent
of the success of the transmis-
sion.
Read/Write accessible always.
TOKINTD
is
H_RESET or S_RESET and is
unaffected by STOP.
cleared
by
14
LTINTEN
Last Transmit Interrupt Enable.
When set to 1, the LTINTEN bit
will cause the Am79C972 control-
ler to read bit 28 of TMD1 as
LTINT. The setting LTINT will de-
termine if TINT will be set at the
end of the transmission.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C972BVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVC\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray 制造商:Advanced Micro Devices 功能描述:5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176 |
| AM79C972BVCW | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BVD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C972BVD\W | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray |
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