參數(shù)資料
型號： AM79C972BKIW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
中文描述： 5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 36/130頁
文件大?。?/td> 1580K
代理商： AM79C972BKIW
36
Am79C972
Basic Non-Burst Write Transfer
By default, the Am79C972 controller uses non-burst
cycles in all bus master write operations. All
Am79C972 controller non-burst write accesses are of
the PCI command type Memory Write (type 7). The
byte enable signals indicate the byte lanes that have
valid data.The Am79C972 controller typically performs
more than one non-burst write transaction within a sin-
gle bus mastership period. FRAME is dropped be-
tween consecutive non-burst write cycles. REQ,
however, stays asserted until FRAME is asserted for
the last transaction. The Am79C972 supports zero wait
state write cycles except with descriptor write transfers.
(See the section
Descriptor DMA Transfers
for the only
exception.) It asserts IRDY immediately after the ad-
dress phase.
Figure 14 shows two non-burst write transactions. The
first transaction has two wait states. The target inserts
one wait state by asserting DEVSEL one clock late and
another wait state by also asserting TRDY one clock
late. The second transaction shows a zero wait state
write cycle. The target asserts DEVSEL and TRDY in
the same cycle as the Am79C972 controller asserts
IRDY.
Basic Burst Write Transfer
The Am79C972 controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
Am79C972 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All Am79C972 control-
ler burst write transfers are of the PCI command type
Memory Write (type 7). AD[1:0] will both be 0 during the
address phase indicating a linear burst order. The byte
enable signals indicate the byte lanes that have valid
data.
The Am79C972 controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The Am79C972 controller
supports zero wait state write cycles except with the
case of descriptor write transfers. (See the section
De-
scriptor DMA Transfers
for the only exception.) The de-
vice asserts IRDY immediately after the address phase
and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 14.
Non-Burst Write Transfer
FRAME
CLK
AD
IRDY
TRDY
C/BE
DEVSEL
REQ
GNT
PAR
DEVSEL is sampled
ADDR
0111
PAR
1
2
3
4
5
6
7
8
10
9
DATA
ADDR
DATA
PAR
PAR
PAR
BE
0111
BE
21485C-17
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C972BVC 制造商:Advanced Micro Devices 功能描述:
AM79C972BVC\W 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray 制造商:Advanced Micro Devices 功能描述:5 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP176
AM79C972BVCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BVD\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BVD\W 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 176-Pin TQFP Tray
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