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| 型號： | IBMN625804GT3B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 256Mb Double Data Rate Synchronous DRAM(256M位雙數(shù)據(jù)速率同步動態(tài)RAM) |
| 中文描述： | 256MB雙數(shù)據(jù)速率同步DRAM（256M位雙數(shù)據(jù)速率同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 9/79頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | IBMN625804GT3B |
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IBMN625404GT3B
IBMN625804GT3B
Preliminary
256Mb Double Data Rate Synchronous DRAM
29L0011.E36997B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 79
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command
to either the base or extended mode registers without affecting the contents of the memory array. The con-
tents of either the mode register or extended mode register can be modified at any valid time during device
operation without affecting the state of the internal address refresh counters used for device refresh.
Register Definition
Mode Register
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Reg-
ister is programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored
information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating either of these requirements results in unspecified opera-
tion.
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable.
The burst length determines the maximum number of column locations that can be accessed for a given
Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the
interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block
if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A
2
-Ai
when the burst length is set to four and by A
3
-Ai when the burst length is set to eight (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. The programmed burst length applies to both Read
and Write bursts.
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