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| 型號： | IBM25PPC750L-DB0A350W |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | IBM25PPC750L-DB0A350W |
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Page 18
Version 2.0
Datasheet
9/30/99
PowerPC 750 SCM RISC Microprocessor
PID8p-750
Preliminary Copy
L2 Bus Output AC Specications
The following table provides the L2 bus output interface AC timing specifications for the PID8p-750 as
defined in Figure 8.
L2 Bus Output Interface AC Timing Specications1
3
Num
Characteristic
L2CR[14-15] is equivalent to:
Unit
Notes
002
01
10
11
Min
Max
Min
Max
Min
Max
Min
Max
26
L2SYNC_IN to output valid -
processor cores at or below 375 MHz
—
3.2
—
3.7
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid -
processor core at 400MHz
—
3.0
—
3.5
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid -
processor core at 433, 450MHz
—
2.6
—
3.1
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid -
processor core at 466 and 500MHz
—
2.4
—
2.9
—
Rsv5
—
Rsv5
ns
27
L2SYNC_IN to output hold
0.5
—
1.0
—
Rsv5
—
Rsv5
—
ns
28
L2SYNC_IN to high impedance
—
3.5
—
4.0
—
Rsv5
—
Rsv5
ns
Note:
1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint voltage of the signal in question. The output timings
are measured at the pins. Midpoint voltage (VM) is 1.4v for (2OVdd) in 3.3v and (2OVdd/2) for all other IO modes, .
2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,
L2CR[14-15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14-15] = 01 is recommended.
3. All maximum timing specifications assume CL = 20pF.
4. This measurement assumes CL= 5pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
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