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參數資料
| 型號： | IBM25PPC750L-DB0A350W |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數： | 11/46頁 |
| 文件大?。?/td> | 610K |
| 代理商： | IBM25PPC750L-DB0A350W |
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9/30/99
Version 2.0
Datasheet
Page 15
PowerPC 750 SCM RISC Microprocessor
Preliminary Copy
PID8p-750
L2 Clock AC Specications
The following table provides the L2CLK output AC timing specifications as defined in Figure 6.
L2CLK Output AC Timing Specications
See Table “Recommended Operating Conditions1,2,3,” on page 6, for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
L2CLK frequency
80
250
MHz
1,5
22
L2CLK cycle time
4.0
12.5
ns
23
L2CLK duty cycle
50
%
2
L2CLK jitter
±150
ps
3,6
Internal DLL-relock time
640
—
L2CLK
4
Note:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The L2CLK frequency to core frequency settings must be chosen such that the
resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. L2CLKOUTA and
L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The total input jitter (short term and long term combined) must be under
± 150ps.
4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time
duration in nanoseconds. Re-lock timing is guaranteed by design and characterization, and is not tested.
5. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
6. Guaranteed by design and characterization, and not tested.
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相關代理商/技術參數 |
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|---|---|
| IBM25PPC750L-DB0A366W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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