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參數資料
| 型號： | IBM25PPC405GPR-3BA333CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 35 MM, PLASTIC, EBGA-456 |
| 文件頁數： | 31/56頁 |
| 文件大?。?/td> | 1095K |
| 代理商： | IBM25PPC405GPR-3BA333CZ |
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Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
37
[TS1O]GPIO3
Odd Trace execution status. To access this function, software
must toggle a DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
[TS2O]GPIO4
Odd Trace execution status. To access this function, software
must toggle a DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
[TS3:6]GPIO5:8
Trace status. To access this function, software must toggle a
DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
[TrcClk]GPIO9
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR bit
or
General Purpose I/O.
Note: Initialization strapping must hold this pin low (0) during
reset.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
Ground pins
GND
Ground
Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16,
and T11-T16 are also thermal balls.
OVDD pins
OVDD
Output driver voltage—3.3V.
VDD pins
VDD
Logic voltage—1.8V.
Other pins
Reserved
Reserved—Except for AF4, do not connect signals, voltage, or
ground to these pins. AF4 must be tied to OVDD or GND.
Signal Functional Description (Part 8 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 45 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 45 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 46.
Signal Name
Description
I/OType
Notes
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相關代理商/技術參數 |
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