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| 型號(hào)： | IBM25PPC405GPR-3BA333CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 333 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 35 MM, PLASTIC, EBGA-456 |
| 文件頁數(shù)： | 30/56頁 |
| 文件大小： | 1095K |
| 代理商： | IBM25PPC405GPR-3BA333CZ |
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Preliminary
PowerPC 405GPr Embedded Processor Data Sheet
36
AGND
Clean Ground input for the PLL.
I
SysErr
Set to 1 when a Machine Check is generated.
O
5V tolerant
3.3V LVTTL
Halt
Halt from external debugger.
I
5V tolerant
3.3V LVTTL
1, 2
GPIO1[TS1E]
GPIO2[TS2E]
General Purpose I/O
or
Even Trace execution status. To access this function, software
must toggle a DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO3[TS1O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO4[TS2O]
General Purpose I/O
or
Odd Trace execution status. To access this function, software
must toggle a DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO5:8[TS3:6]
General Purpose I/O
or
Trace status. To access this function, software must toggle a
DCR bit.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO9[TrcClk]
General Purpose I/O
or
Trace interface clock. A toggling signal that is always half of the
CPU core frequency. To access this function, software must
toggle a DCR bit.
Note: Initialization strapping must hold this pin low (0) during
reset.
I/O[O]
5V tolerant
3.3V LVTTL
1, 6
GPIO24
General Purpose I/O.
Note: The pull-up initialization strapping resistor must be 1 k
rather than 3k
in order to overcome the internal pull-down
resistor.
I/O
3.3V LVTTL
w/pull-down
1, 6
TestEn
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
I
1.8V CMOS
w/pull-down
TmrClk
An external clock input that can be used to clock the timers in the
CPU core.
I
5V tolerant
3.3V LVTTL
1
Trace Interface
[TS1E]GPIO1
[TS2E]GPIO2
Even Trace execution status. To access this function, software
must toggle a DCR bit
or
General Purpose I/O.
O[I/O]
5V tolerant
3.3V LVTTL
1, 6
Signal Functional Description (Part 7 of 8)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 45 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 45 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 46.
Signal Name
Description
I/OType
Notes
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|---|---|
| IBM25PPC405GPR3DB400Z | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456 |
| IBM25PPC405GPR3BB400Z | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA456 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC405GPR3BB266 | 制造商:IBM 功能描述: |
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| IBM25PPC405GPR-3KB266C | 制造商:IBM 功能描述: |
| IBM25PPC440GX3CB667C | 制造商:IBM 功能描述: |
| IBM25PPC603E-BX-080-X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:32-Bit Microprocessor |
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