參數(shù)資料
型號(hào)： IBM25NPE405L-3FA200CZ
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324
封裝： 23 X 23 MM, PLASTIC, EBGA-324
文件頁數(shù)： 46/52頁
文件大?。?/td> 907K
代理商： IBM25NPE405L-3FA200CZ
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
50
Trace Interface
[TrcClk]
n/a
8.7
1.2
12
8
[TS1E]
n/a
5.8
1.2
12
8
[TS2E]
n/a
5.7
1.2
12
8
[TS1O]
n/a
5.3
1
12
8
[TS2O]
n/a
5.3
1
12
8
[TS3:6]
n/a
5.4
1
12
8
SDRAM Interface
BA1:0
n/a
5.5
1.5
19
12
SysClk
1, 2
BankSe3:0
n/a
4.6
1
19
12
SysClk
2
CAS
n/a
5.3
1.4
19
12
SysClk
1, 2
ClkEn0:1
n/a
3.9
1
40
25
SysClk
2
DQM0:3
n/a
4.7
1
19
12
SysClk
2
DQMCB
n/a
4.7
1
19
12
SysClk
2
ECC0:7
1.8
0.3
4.5
1
19
12
SysClk
2
MemAddr12:00
n/a
5.5
1.4
19
12
SysClk
1, 2
MemClkOut0:1
n/a
0.4
-1.2
19
12
SysClk
2, 3
MemData00:31
1.8
0.3
4.4
1
19
12
SysClk
2
RAS
n/a
5.7
1.6
19
12
SysClk
1, 2
WE
n/a
5.4
1.4
19
12
SysClk
1, 2
External Peripheral Bus Interface
[DMAReq0:3]
4.1
0
5.5
1.1
n/a
PerClk
[DMAAck0:3]
n/a
5.9
1.1
12
8
PerClk
[EOT0:3/TC0:3]
3.7
-0.1
6.7
1.2
12
8
PerClk
PerAddr04:31
n/a
6.5
0.9
17
11
PerClk
PerBLast
n/a
5.6
1.4
12
8
PerClk
PerCS0:3
n/a
5.5
1.3
12
8
PerClk
PerData00:15
3.9
1
7.1
1
17
11
PerClk
PerOE
n/a
5.7
1.4
12
8
PerClk
PerPar0:1
2.7
0
6.4
0.9
17
11
PerClk
PerR/W
n/a
5.7
1.4
12
8
PerClk
PerReady
6.2
-0.5
n/a
PerClk
PerWBE0:1
n/a
5.7
1.3
12
8
PerClk
n/a
0.5
-0.9
17
11
PLB Clk
4
PerErr
3.5
-0.6
n/a
PerClk
[PerWE]
n/a
7
1.3
12
8
I/O Specifications—266MHz (Part 2 of 2)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM. Output times in table are in cycle 1.
3. SDRAM I/O timings are specified relative to a SysClk terminated in a lumped 10pF load.
4. SDRAM interface hold times are guaranteed at the NPe405L package pin. System designers must use the NPe405L
IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and
reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
5. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(maximum)
I/O L
(minimum)
相關(guān)PDF資料
PDF描述
IBM25NPE405L-3FA266CZ 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IBM25NPE405L-3FA266C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP
IBM25NPE405L-3FA266CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP
IBM25PPC403GAJC33C1 制造商:IBM 功能描述:
IBM25PPC405CR-3BC200C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|316PIN|PLASTIC
IBM25PPC405CR-3BC200CZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|316PIN|PLASTIC
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