- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67682 > IBM25NPE405L-3FA200CZ 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 PDF資料下載
參數(shù)資料
| 型號： | IBM25NPE405L-3FA200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 X 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 29/52頁 |
| 文件大?。?/td> | 907K |
| 代理商： | IBM25NPE405L-3FA200CZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當(dāng)前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
35
[DMAReq0:3]
DMA request. Used by peripherals to request a data
transfer. Following a system reset, the default mode of the
signals is active-low. They may be programmed to active-
high using the DMA0_POL register.
I
5V tolerant
3.3V LVTTL
1
[DMAAck0:3]
DMA acknowledge. Used to indicate to peripherals that
data transfer is complete. Following a system reset, the
default mode of the signals is active-low. They may be
programmed to active-high using the DMA0_POL register.
O
5V tolerant
3.3V LVTTL
[EOT0:3/TC0:3]
End Of Transfer/Terminal Count. Indication by peripherals
that all data has been transfered, or by DMA controller that
programmed amount of data has been transfered.
Following a system reset, the default mode of the signals is
active-low. They may be programmed to active-high using
the DMA0_POL register.
I/O
5V tolerant
3.3V LVTTL
1
Internal Peripheral Interface
UARTSerClk
Serial Clock used to provide an alternative clock to the
internally generated serial clock. Used in cases where the
allowable internally generated baud rates are not
satisfactory. This input can be individually connected to
either or both UART0 and UART1.
I
5V tolerant
3.3V LVTTL
1
UART0_Rx
UART0 Receive data.
I
5V tolerant
3.3V LVTTL
1
UART0_Tx
UART0 Transmit data.
O
5V tolerant
3.3V LVTTL
[UART0_DCD]
UART0 Data Carrier Detect.
I
5V tolerant
3.3V LVTTL
1
[UART0_DSR]
UART0 Data Set Ready.
I
5V tolerant
3.3V LVTTL
1
[UART0_CTS]
UART0 Clear To Send.
I
5V tolerant
3.3V LVTTL
1
[UART0_DTR]
UART0 Data Terminal Ready.
O
5V tolerant
3.3V LVTTL
[UART0_RTS]
UART0 Request To Send.
O
5V tolerant
3.3V LVTTL
[UART0_RI]
UART0 Ring Indicator.
I
5V tolerant
3.3V LVTTL r
1
Signal Functional Description (Part 4 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25NPE405L-3FA266CZ | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324 |
| IBM25PPC405EP-3GB133CZ | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405EP-3GB133C | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
| IBM25PPC405GP-3DD200C | RISC PROCESSOR, PBGA456 |
| IBM25PPC405GP-3BD266C | RISC PROCESSOR, PBGA456 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25PPC403GAJC33C1 | 制造商:IBM 功能描述: |
| IBM25PPC405CR-3BC200C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|316PIN|PLASTIC |
| IBM25PPC405CR-3BC200CZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|316PIN|PLASTIC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。