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| 型號： | IBM25NPE405L-3FA200CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| 封裝： | 23 X 23 MM, PLASTIC, EBGA-324 |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 907K |
| 代理商： | IBM25NPE405L-3FA200CZ |
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Preliminary
PowerNP NPe405L Embedded Processor Data Sheet
34
ECC0:7
ECC check bits 0:7.
I/O
3.3V LVTTL
BankSel0:3
Select up to four external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases,
glueless SDRAM attachment without requiring this signal
to be repowered by a PLL or zero-delay buffer.
O3.3V LVTTL
External Peripheral Bus Interface
PerData00:15
External peripheral data bus .
Note: PerData00 is the most significant bit (msb) on this
bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr04:31
External peripheral address bus .
O
5V tolerant
3.3V LVTTL
PerPar0:1
External peripheral byte parity signals.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:1
Peripheral write-bte enable. Byte-enables which are valid
for an entire cycle or write-byte-enables which are valid for
each byte on each data transfer, allowing partial word
transactions. Used by either external bus controller or DMA
controller depending upon the type of transfer involved.
O
5V tolerant
3.3V LVTTL
2, 7
[PerWE]
Peripheral write enable. Low when any of the two PerWBE
signals are low.
I/O
5V tolerant
3.3V LVTTL
7
PerCS0:3
Peripheral Chip Selects
O
5V tolerant
3.3V LVTTL
PerOE
Peripheral output enable. Used by either the external bus
controller or the DMA controller depending upon the type
of transfer involved. When the NPe405L is the bus master,
it enables the peripherals to drive the bus.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Peripheral read/write. Used by either the external bus
controller or DMA controller depending upon the type of
transfer involved. High indicates a read from memory, low
indicates a write to memory.
O
5V tolerant
3.3V LVTTL
PerReady
Indicates peripheral is ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
PerBLast
Peripheral burst last. Used to indicate the last transfer of a
memory access.
O
5V tolerant
3.3V LVTTL
7
PerClk
Peripheral Clock. Used by synchronous peripherals.
O
5V tolerant
3.3V LVTTL
PerErr
Used to indicate errors from peripherals.
I
5V tolerant
3.3V LVTTL
1, 5
Signal Functional Description (Part 3 of 6)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 30 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 31.
Signal Name
Description
I/O
Type
Notes
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
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| IBM25PPC405CR-3BC200CZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|316PIN|PLASTIC |
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