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參數(shù)資料
| 型號： | IBM25EMPPC740EBUF2000 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 29/43頁 |
| 文件大?。?/td> | 431K |
| 代理商： | IBM25EMPPC740EBUF2000 |
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Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
35 of 43
7.6 Pull-up Resistor Requirements
The PPC740 and PPC750 require high -resistive (weak: 10 K
) pull-up resistors on sev-
eral control signals of the bus interface to maintain the control signals in the negated
state after they have been actively negated and released by the PPC740 and PPC750 or
other bus masters. These signals are -- TS, ABB, DBB, and ARTRY.
In addition, the PPC750 has one open-drain style output that requires a pull-up resis-
tor (weak or stronger: 4.7 K
-1-K) if it is used by the system. This signal is --
CKSTP_OUT.
During inactive periods on the bus, the address and transfer attributes on the bus are
not driven by any master and may oat in the high-impedance state for relatively long
periods of time. Since the PPC740 and PPC750 must continually monitor these signals
for snooping, this oat condition may cause excessive power draw by the input receiv-
ers on the processor or by other receivers in the system. It is recommended that these
signals be pulled up through weak (10 K
) pull-up resistors or restored in some man-
ner by the system, The snooped address and transfer attribute inputs are -- A[0-31],
AP[0-3], TT[0-4], TBST, and GBL.
The data bus input receivers are normally turned off when no read operation is in
progress and do not require pull-up resistors on the data bus. Other data bus receivers
in the system, however, may require pull-ups, or that those signals be otherwise driven
by the system during inactive periods. The data bus signals are -- DH[0-31], DL[0-31],
and DP[0-7].
If address or data parity is not used by the system, and the respective parity checking
is disabled through HID0, the input receivers for those pins are disabled, and those
pins do not require pull-up resistors and should be left unconnected by the system. If
all parity generation is disabled through HID0, than all parity checking should also be
disabled through HID0, and all parity pins may be left unconnected by the system.
No pull-up resistors are normally required for the L2 interface.
7.7 Thermal Management Information
This section provides thermal management information for the CBGA package for air
cooled applications. Proper thermal control design is primarily dependent upon the
system-level design; that is, the heat sink, air ow and the thermal interface material.
To reduce the die-junction temperature, heat sinks may be attached to the package by
several methods -- adhesive, spring clip to holes in the printed-circuit board or pack-
age, and mounting clip and screw assembly; see Figure 19 . This spring force should
not exceed 5.5 pounds.
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